This file is raw output from pdftotext and may not be ideal for distribution. If you are a maintainer for Hackipedia, please sit down when you have time and clean this text version up. Source PDF: /mnt/fw-js/docs/Hardware/TV Video Encoders/Gec Plessy/VP536A-VP536B NTSC-PAL DIGITAL VIDEO ENCODER.pdf Like all conversions the text below should be fully readable as UTF-8 unicode text. --------------------------------------------------------------- SEPTEMBER 1994 ADVANCE INFORMATION DS3925 - 2.1 VP536A/VP536B* NTSC/PAL DIGITAL VIDEO ENCODER (supersedes DS3925 - 1.2, March 1994 & MS4013 - 1.0 July 1994) FEATURES DESCRIPTION s Converts RGB data (3x8bits) to analog composite The VP536A/VP536B converts digital RGB data video and S-video (3x8bits) into analog NTSC/PAL (NTSC only for VP536A) composite video and S-video signals. The outputs are s Internal video timing generation capable of driving doubly terminated 75 ohm loads with s RGB or YUV input modes standard video levels. The device will also accept gamma-corrected RGB data s Progressive scanning (non-interlaced fields) or YUV data. Progressive scan (non-interlaced fields) video display mode optional display mode is available. s Separate horizontal and vertical sync outputs The output pixel rate is approximately 7 times Fsc (color s 68 pin PLCC package subcarrier frequency) for NTSC (6.6 times Fsc for PAL) which is approximately 25MHz. Input pixel rate is half this s Better than 9 bit video accuracy frequency; approximately 12.5MHz. All the necessary synchronization signals are generated internally. Digital horizontal and vertical sync outputs are APPLICATIONS available for use by the host system. The rise and fall times of sync, burst envelope and video s Multi-media blanking are internally controlled to be within composite video specifications. s Video Games Two digital to analog converters (DACs) are used to s PC’s convert the digital luminance and chrominance data into s Graphics analog signals. An inverted composite video signal is generated by summing the complimentary current outputs of s Display Adaptors each DAC. An internally generated reference voltage s Video Effects Processors provides the biasing for the DACs. CTRLB1 CTRLB2 VS COMPOSITE SYNC VIDEO TIMING GENERATOR HS SET-UP MATRIX BYPASS BURST GATE LUMAOUT (SIN X/X)-1 R0:7 Y LUMA INTERPOLATOR PRECOMPENSATION DAC RGB COMP- G0:7 TO OUTB YUV MATRIX U CHROMA B0:7 INTER- BANDPASS LOW-PASS MODULATOR CHROMA POLATOR FILTER DAC V FILTER CHROMAOUT COLOR SUBCARRIER GENERATOR CLK25I CLK12I CLK25O CLK12O CTRLA1 CTRLA2 CTRLA3 Fig. 1. Functional Block Diagram * VP536A OPERATES IN NTSC ONLY. VP536B OPERATES IN BOTH NTSC AND PAL MODES. VP536B IS A FUTURE DEVELOPMENT. VP536A/VP536B NTSC/PAL Video Standards Input Pixel Data Format Both NTSC (4-field, 525 lines) and PAL (8-field, 625 Input pixel data may be in one of two formats; gamma lines) video standards are supported by the VP536B (NTSC corrected RGB and YUV. This format is controlled by the only for VP536A). All raster synchronization, color subcarrier state of the pins CTRLA1, CTRLA2 and CTRLA3 according and burst characteristics are adapted to the standard to the following table. selected. However, different input clock frequencies are necessary for each of the two video standards. For the NTSC mode of operation, input clock frequencies of CTRLA2 CTRLA1 Input Pixel Data Format 25.048948MHz. and 12.524474MHz. are required. For the PAL mode of operation on the VP536B, the required input 0 0 reserved clock frequencies are 29.500000MHz. and 14.750000MHz. The mode of operation is selected through the CTRLB1 0 1 RGB (gamma corrected) and CTRLB2 pins as shown in Table 1. 1 0 YUV Progressive Scan Display 1 1 reserved Progressive scanning (non-interlaced fields) display Table 2: Input Pixel Data Format modes are available for both semi-NTSC and semi-PAL video applications. In both cases, field 1 is repeated while NOTE: CTRLA1 is internally pulled high, while CTRLA2 & CTRLA3 field 2 is discarded. An extra half line is included in field 1. are internally pulled low; therefore if left unconnected, gamma cor- Thus in the semi-NTSC mode, 263 lines of field 2 are rected RGB is the default input pixel data format. CTRLA3 is reserved. retraced as field 1 resulting in 526 lines per frame, and similarly in the semi-PAL mode, 313 lines of field 2 are re- traced as field 1 resulting in 626 lines per frame. The RGB input data coding is straight binary and is in Progressive scanning display mode is selected through the range of 0-255. In the YUV input mode, Y, U and V data is the CTRLB1 and CTRLB2 pins as shown in Table 1. presented on the R, B and G input data buses, respectively. Y data coding is binary and is in the range of 0-247. U and V coding is in two’s complement binary. U is in the range of - CTRLB2 CTRLB1 Video Standard 102 to +102 and V is in the range of -107 to +107. 0 0 NTSC Video Blanking 0 1 Progressive Scan NTSC The VP536A/VP536B automatically performs standard composite video blanking. Lines 1-17, 261-279, 523-525 1 0 PAL(VP536B only) inclusive, as well as the last half of line 260 and the first half of line 280 are blanked in the NTSC mode. In PAL mode on Progressive Scan PAL 1 1 the VP536B, lines 1-22, 311-335, 624-625 inclusive, as well (VP536B only) as the last half of line 623 and the first half of line 23 are Table 1: VP536A/VP536B Modes of Operation blanked. NOTE: CTRLB1 & CTRLB2 are internally pulled low, therefore, if left The host pixel data can be phased relative to the active unconnected, NTSC is the default mode of operation. video timing by counting the CLK12I clock periods from the rising edge of HS. NTSC active video starts 48 CLK12I clock Video Timing cycles after the rising edge of the horizontal sync pulse The VP536A/VP536B has an internal sync generator output, and PAL active video starts 58 CLK12I clock periods which produces video timing signals appropriate to the mode after the rising edge of HS (HS and VS pulse edges coincide of operation. All timing signals are derived from the two input with the rising edge of the CLK12I clock). clocks. These clocks are input on the CLK25I pin and the Input pixel data is ignored during the composite CLK12I pin. The two input clock frequencies for NTSC and blanking periods. PAL are related by a ratio of 2. The lower frequency corresponds to the input pixel data Color Space Matrix rate. Input pixel data is latched in on the rising edge of the CLK12I clock. The RGB color space is converted to a YUV color The clocks must be derived from a crystal controlled space, using a transformation matrix defined by the NTSC oscillator in order to avoid timing, chroma frequency and and PAL colorimetry definitions. If the input data format is modulation errors. YUV, this block is bypassed without affecting the overall data The video timing generator produces the internal latency. composite sync, blanking and burst gate as well as externally available horizontal sync (HS) and vertical sync (VS) pulse signals. The HS and VS signals are negative true pulses coincident with the sync pulses in the output video signals. The HS signal has the same duration as a standard horizontal sync pulse but is continuous through the vertical sync interval. 2 VP536A/VP536B Interpolator Luminance, Chrominance & Composite Video Outputs The luminance and chrominance data is separately passed through interpolating filters to produce output The Luminance video output (LUMAOUT pin) drives a sampling rates double that of the incoming pixel rate. This 37.5 ohm load at 1.0V, sync tip to peak white. It contains only reduces the sinx/x distortion that is inherent in the digital to the image’s luminance content plus the composite analog converters and also simplifies the analog synchronization pulses. In the NTSC mode, a Set-Up Level reconstruction filter requirements. offset is added during the active video portion of the raster. Sinx/x Distortion Precompensation The chrominance video output (CHROMAOUT pin) The luminance data is precompensated for the sinx/x drives a 37.5 ohm load at levels proportional in amplitude to distortion that is inherent in the digital to analog converters. the luma output (40 IRE pk-pk burst). This output has a fixed Since the chrominance data is contained within a relatively offset current which will produce approximately a 0.5V DC narrow frequency range, it’s sinx/x distortion is compensated bias across the 37.5 ohm load. Burst is injected with for by increasing the gain of the chrominance DAC by a fixed appropriate timing relative to the luma signal. amount. Luma, Chroma and true Composite video signals may Digital To Analog Converters be obtained simultaneously through the use of an external inverting video amplifier with the inverted composite video The VP536A/VP536B contains two 8-bit digital to output (COMPOUTB pin). analog converters which produce the analog video signals. The DACs use a current steering architecture in which bit currents are routed to one of two outputs; thus each DAC The inverted composite video output has a fixed DC has a true and complimentary output. The use of identical offset. Sync tip is the most positive voltage and is current sources and current steering their outputs means approximately 1.5V with a 37.5 ohm load. that monotonicity is guaranteed. An on-chip voltage reference of 1.0V (typ.) provides the necessary biasing. However, the VP536A/VP536B may be used in applications The NTSC output video waveforms of the luma, chroma where an external 1V reference is provided, to adjust the and inverted composite signals for 100% amplitude, 100% video levels. In this case the external reference should be temperature compensated and provide a low impedance saturated color bars are shown in Figs. 3-5. output. The full-scale output currents of the DACs is set by Extendable S-Video Bandwidth external resistors between the LUMAGAIN, CHROMAGAIN and GND pins. An on-chip loop amplifier stabilizes the full- The bandwidth of color baseband signals is typically scale output current against temperature and power supply limited in order to avoid modulation problems that develop in variations. composite video as the bandwidth approaches that of the By summing the complimentary current outputs of the subcarrier frequency. The VP536A/VP536B can use either two DACs, an inverted composite video signal is obtained. traditional bandwidth limited or extended bandwidth Note that this signal has a DC offset. The analog outputs of baseband signals. For applications where the composite the VP536A/VP536B are capable of directly driving a 37.5 signal is the main source of the video display, it is ohm load, such as a doubly terminated 75 ohm co-axial recommended that bandwidth limiting be used in order to cable. avoid “dot-crawl” effects in the display. For S-Video applications where the luma and chroma signals are DAC Gain Adjust separate, enabling the extended bandwidth will result in improved picture definition. The gains of the luma and chroma DACs are The enabling/disabling of this bandwidth extension is independently adjustable. The gains are adjusted using the controlled through the TCSPK pin as shown below. external gain setting resistors between the LUMAGAIN, CHROMAGAIN pins and GND. For the correct DAC gains in the NTSC mode, the TCSPK Chroma Bandwidth LUMAGAIN resistance should be 905ohms. The CHROMAGAIN resistance should be 562ohms for the 0 Extended Bandwidth proper corresponding chroma amplitude (including sinx/x compensation). 1 Limited Bandwidth For the correct DAC gains in the PAL mode on VP536B, Table 3: Bandwidth Control the LUMAGAIN resistance should be 837ohms and the CHROMAGAIN resistance should be 520ohms for the NOTE: TCSPK is internally pulled LOW, therefore proper corresponding chroma amplitude (including sinx/x Extended Bandwidth is the default selection. compensation). 3 VP536A/VP536B Master Reset Video Timing Reset The VP536A/VP536B also features the ability to The VP536A/VP536B can be initialized with the RESET independently reset the video timing generator without pin. This is an active low signal and must be active for a affecting the data path. The TSURST pin controls this minimum of 2 CLK12I clock periods in order for the function. Taking this pin high resets the video timing VP536A/VP536B to be reset. The device resets to line 64, generator. If this pin is left open, it is internally pulled low. start of horizontal sync (ie line blanking active). There is no This feature can be usefull here two independent video on-chip power on reset circuitry. sources are used. 48 Periods CLK12I HS Line 1 Line 2 Line 3 Line 4 Line 17 VS Field 1 Line 17 RGB/YUV INPUT DATA 1st 2nd pixel pixel Fig. 2a. NTSC Input Timing Diagram 58Periods CLK12I HS Line 1 Line 2 Line 3 Line 4 Line 23 VS Field 1 Line 23 RGB/YUV INPUT DATA 1st 2nd pixel pixel Fig. 2b. PAL Input Timing Diagram for VP536B NOTE: 1. Coincident falling edges of HS and VS denote the start of an odd field. 2. VS is low during the first 3 lines in each NTSC field and during the first 21/2 lines in each PAL field. 3. Input pixel data is ignored during composite blanking periods. 4 VP536A/VP536B Fig. 3. MAGENTA NTSC Luminance Video Output YELLOW GREEN BLACK WHITE Waveform CYAN BLUE RED 100% saturation, 100% amplitude mA V color bars. 26.67 1.000 WHITE LEVEL LUMAGAIN resistor = 905 ohms, VREF=1.0V, 37.5ohm load. typical current values 100 IRE BLACK LEVEL 9.07 0.340 7.5 IRE 7.63 0.286 BLANK LEVEL 40 IRE SYNC LEVEL 0.00 0.000 Fig. 4. NTSC Chrominance Video Output MAGENTA Waveform YELLOW GREEN BLACK WHITE CYAN BLUE RED 100% saturation, 100% amplitude mA V color bars. 25.35 0.951 CHROMAGAIN resistor = 562ohms, VREF=1.0V, 37.5ohm load. typical current values 18.04 0.677 20 IRE BLANK 14.23 0.534 20 IRE LEVEL 10.42 0.391 COLOR BURST 3.11 0.117 Fig. 5. NTSC Inverted Composite Video Output Waveform MAGENTA YELLOW 100% saturation, 100% amplitude GREEN BLACK WHITE mA mA V V CYAN BLUE color bars. RED LUMAGAIN resistor = 905 ohms, 40.79 1.530 40 IRE CHROMAGAIN resistor = 562ohms, 37.62 1.411 36.97 1.386 VREF=1.0V, 37.5ohm load 20 IRE typical current values 33.16 1.244 20 IRE 7.5 IRE 31.72 1.190 29.35 1.101 100 IRE 14.12 0.530 31 IRE 8.23 0.309 5 VP536A/VP536B Pin Descriptions Pin Name Pin No. Description 8 Bit Blue data inputs. B0 is the least significant bit, corresponding to Pin 2. These pins are internally pulled B0-B7 2-9 low. G0-G7 17-24 8 Bit Green data inputs. G0 is the least significant bit. These pins are internally pulled low. G0 is pin 17 8 Bit Red data inputs. R7 is the most significant bit corresponding to Pin 1. These pins are internally pulled R0-R7 62-68, 1 low. 2X pixel rate clock input. The VP536A/VP536B requires a clock whose frequency is twice the input pixel data rate; i.e., 25.0489484MHz. for the NTSC mode of operation, and with the VP536B, 29.500000MHz. for the CLK25I 57 PAL mode of operation.This clock must be derived from a crystal controlled oscillator in order to avoid chroma frequency, modulation and timing errors. CLK12I 60 Pixel rate clock input. The frequency of this clock must be exactly half that of the CLK25I clock. 2X pixel rate clock output. The CLK25I clock is output on this pin. Note that this output clock signal is inverted CLK25O 61 with respect to the CLK25I clock. CLK12O 51 Pixel rate clock output. The CLK12I clock is output on this pin. Horizontal sync pulse output. This is an active low signal output, i.e. the presence of a sync pulse is denoted HS 14 by the signal being low. VS 13 Vertical sync pulse output. This is an active low signal output. VP536A/VP536B master reset. This is an active low input signal and must be asserted for a minimum of 2 RESET 16 CLK12I clock periods in order to reset the VP536A/VP536B. Input data format control. Control codes on these three input pins determine the format of the input data as CTRLA1 59 described in Input Pixel Data Format on Page 2. CTRLA1 is internally pulled high, while CTRLA2 and CTRLA2 58 CTRLA3 are internally pulled low; therefore if left open, the default input data format is gamma corrected CTRLA3 54 RGB. Video standard control. Control codes on these two input pins determine the video display mode as CTRLB1 52 described in Table 2 on Page 2. These pins are internally pulled low, therefore if left open, the default video CTRLB2 53 display mode is NTSC. Enable/Disable extended video bandwidth. Taking this pin high limits the bandwidth of the video signal as TCSPK 49 described in Extendable S-Video Bandwidth on Page 3. This pin is internally pulled low, therefore if left open, extended bandwidth is enabled. Synchronous reset of video timing. An active high pulse on this pin resets the video timing generator without TSURST 50 affecting the data path. On the rising edge of CLK12I following TSURST going low, Field 1, line 1 is initiated. This pin is internally pulled low. Voltage reference output. This output is nominally 1.0V and should be decoupled with a 0.1uF capacitor to VREF 28 GND. LUMA- 30 Luma DAC compensation. A 0.1uF ceramic capacitor must be connected between pin 30 and pin 31. COMP CHROMA- 38 Chroma DAC compensation. A 0.1uF ceramic capacitor must be connected between pin 38 and pin 37. COMP LUMAOUT 32 Luminance, inverted composite and chrominance video signal outputs. These outputs are high impedance COMPOUTB 34 current source outputs. A DC path to GND must exist from each of these pins. CHROMAOUT 36 Luminance full scale current control. A resistor connected between this pin and GND sets the magnitude of the luminance video output current. An internal loop amplifier controls a reference current flowing through LUMAGAIN 29 this resistor so that the voltage across it is equal to the Vref voltage. This reference current has a weighting equal to 16 LSB’s. Note that the IRE relationships shown in Fig. 3 are maintained, regardless of the output full scale current. Table 4: Pin Descriptions 6 VP536A/VP536B Pin Name Pin No. Description Chrominance full scale current control. As with the LUMAGAIN pin, a resistor between this pin and GND controls the magnitude of the chrominance video signal. An internal loop amplifier adjusts a reference current CHROMAGAIN 39 flowing through this resistor so that the voltage across it is equal to the Vref voltage. This reference current has a weighting equal to 16 LSB’s. TEST0-TEST7 41-48 These pins must be tied low. CTRLC1 15 Test mode control. These two pins are used to configure the VP536A/VP536B into various test modes. They CTRLC2 12 should be held low during normal operation. 10, 25, VAA 31, 37, Positive supply input. All VAA pins must be connected. 40, 55 11, 26, 56 GND Negative supply input (GND). All GND pins must be connected. 27, 33, 35 Table 4: Pin Descriptions (Continued) 7 VP536A/VP536B RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min. Typ. Max. Units Power supply voltage VAA 4.75 5.00 5.25 V Power supply current IAA 200 mA Input clock frequency CLK25I (NTSC) 25.048948 MHz. CLK12I (NTSC) 12.524474 MHz. CLK25I (PAL - VP536B) 29.500000 MHz. CLK12I (PAL - VP536B) 14.750000 MHz. CLK25I & CLK12I rising edges must be synchronous Input clock frequency accuracy 25 ppm Analog video output load 37.5 Ω Gain resistors Lumagain resistor (NTSC) 905 Ω Chromagain resistor (NTSC) 562 Ω Lumagain resistor (PAL - VP536B) 837 Ω Chromagain resistor (PAL - VP536B) 520 Ω Ambient operating temperature 0 70 o C ABSOLUTE MAXIMUM RATINGS (Referenced to GND) Parameter Symbol Min. Typ. Max. Units Power supply VAA -0.3 7 V Voltage on any non-power pin -0.3 VAA + 0.3 V Analog video output short circuit duration Indefinite oC Ambient operating temperature 0 70 o Storage temperature -55 125 C NOTE: Stresses exceeding those listed under Absolute Maximum Ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. 8 VP536A/VP536B ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions DC Characteristics (see note on Page 11) Parameter Symbol Min. Typ. Max. Units Resolution (each DAC) 8 Bits Accuracy (each DAC) Integral linearity error INL +/- 1.5 LSB Differential linearity error DNL +/- 1 LSB Gray scale error +/- 5 % gray scale Monotonicity Guaranteed Analog video output compliance VAVOC -0.3 1.6 V Digital Inputs Input high voltage VIH 3.0 V Input low voltage VIL 0.8 V Digital Outputs Output high voltage (IOH = -10.0 mA) VOH VAA - 1 V Output low voltage (IOL = 10.0 mA) VOL 0.4 V Luminance video output current White level relative to black level (NTSC) 16.74 17.6 18.46 mA 255 LSB Black level relative to blank level (NTSC) 0.95 1.44 1.90 mA 21 LSB Blank level relative to sync level (NTSC) 6.30 7.63 8.96 mA 111 LSB LSB size (NTSC) 69.1 µA White level relative to black/blank level (PAL -VP536B) tbd Black/blank level relative to sync level (PAL -VP536B) tbd LSB size (PAL -VP536B) tbd Chrominance video output current Blank level (NTSC) 13.51 14.23 14.95 mA Peak chroma level relative to blank level (NTSC) +/- 10.12 +/- 11.12 +/- 12.12 mA (corresponding to 100% saturated red) Peak burst level relative to blank level (NTSC) +/- 3.46 +/- 3.81 +/- 4.16 mA LSB size (NTSC) 111.2 µA Blank level (PAL -VP536B) tbd Peak chroma level relative to blank level (PAL) tbd (corresponding to 100% saturated red) (-VP536B) Peak burst level relative to blank level (PAL -VP536B) tbd LSB size (PAL -VP536B) tbd Internal reference voltage VREF 0.95 1.00 1.05 V Internal reference voltage output impedance tbd KΩ 9 VP536A/VP536B AC Characteristics (see note on Page 11) Rise and fall times are measured between 10% and 90% of the final values Parameter Symbol Min. Typ. Max. Units CLK12I clock delay with respect to CLK25I clock tdCLK 2 18 ns Note 1 Data set-up time (wrt CLK12I clock) tsuDATA 8 ns Data hold time (wrt CLK12I clock) thDATA 5 ns HS/VS output delay wrt CLK12I clock tdSYNC 0 20 ns HS low pulse width (NTSC) twHS-NTSC 59 CLK12I cycles HS low pulse width (PAL -VP536B) twHS-PAL tbd CLK12I cycles VS low pulse width(NTSC) twVS-NTSC 2388 CLK12I cycles VS low pulse width (PAL -VP536B) twVS-PAL tbd CLK12I cycles Input clock pulse width high time 16 ns Input clock pulse width low time 16 ns Analog video output delay (wrt CLK25I clock) tdAVO 10 ns Analog video output rise/fall time trfAVO 8 ns Analog video output settling time (50% to +/- 1 LSB) tsAVO 12 ns Glitch impulse 100 pV-sec Signal related harmonics of DAC outputs for 1MHz. direct digitally synthesized sine wave tbd dB Pipeline delay (data in to analog video out) tbd Power supply rejection ratio 40 dB (chromacomp, lumacomp = 0.1uF, f = 1 KHz.) Note 1 Tests are taken at 50% duty cycle on CLK12I and CLK25I. Timing Waveforms CLK25I tdCLK CLK12I thDATA tsuDATA RGB DATA tdSYNC HS/VS tdAVO tsAVO twHS twVS LUMAOUT, CHROMAOUT, COMPOUTB trfAVO Fig. 6. Input/Output Timing Diagram 10 VP536A/VP536B Video Characteristics (see note below) Rise and fall times are measured between 10% and 90% of the final values Parameter Symbol Min. Typ. Max. Units Luminance bandwidth (Extended Bw mode) 4.0 MHz. Luminance bandwidth (Reduced Bw mode) 2.5 MHz. Chrominance bandwidth (Extended Bw mode) 1.8 MHz. Chrominance bandwidth (Reduced Bw mode) 1.2 MHz. Burst frequency (NTSC) 3.579545 MHz. Burst frequency (PAL -VP536B) 4.433619 MHz. Burst cycles (NTSC) 10 Fsc cycles Burst cycles (PAL -VP536B) 10 Fsc cycles Burst envelope rise/fall time 1.5 Fsc cycles Analog video sync rise/fall time 90 ns Analog video blank rise/fall time 160 ns Differential gain 1.5 % pk-pk o Differential phase 1.0 pk-pk Signal to Noise Ratio (white field) 60 dB Chroma AM signal to noise ratio (100% red field) 58 dB Chroma PM signal to noise ratio (100% red field) 56 dB Hue accuracy 2.5 % Color saturation accuracy 2.5 % Residual subcarrier -60 dB Luminance/chrominance delay 20 ns NOTE: The DC, AC and Video characteristics listed above are based on design targets and/or actual measurements on a limited number of devices. All parametric information is subject to review following further characterization. 11 VP536A/VP536B Pin Pin Pin Pin No. Name No. Name 1 R7 35 GND 2 B0 36 CHROMAOUT 3 B1 37 VAA 4 B2 38 CHROMACOMP 5 B3 39 CHROMAGAIN 6 B4 40 VAA 7 B5 41 TEST0 8 B6 42 TEST1 9 B7 43 TEST2 10 VAA 44 TEST3 11 GND 45 TEST4 12 CTRLC2 46 TEST5 13 VS 47 TEST6 14 HS 48 TEST7 15 CTRLC1 49 TCSPK 16 RESET 50 TSURST 17 G0 51 CLK12O 18 G1 52 CTRLB1 19 G2 53 CTRLB2 20 G3 54 CTRLA3 21 G4 55 VAA 22 G5 56 GND 23 G6 57 CLK25I 24 G7 58 CTRLA2 25 VAA 59 CTRLA1 26 GND 60 CLK12I 27 GND 61 CLK25O 28 VREF 62 R0 29 LUMAGAIN 63 R1 30 LUMACOMP 64 R2 31 VAA 65 R3 32 LUMAOUT 66 R4 33 GND 67 R5 34 COMPOUTB 68 R6 12 FERRITE POWER BEAD + 100µF 9 1 68 0.1µ 11 59 GND 12 58 56 0.1µ 15 54 VP536A/B 52 50 48 46 25 2.7µH 220µF 0.1µ + S-VIDEO 27 29 31 33 35 37 39 40 42 44 CHROMA 75 470pF 470pF 0.1µ 0.1µ GND 2.7µH 220µF + S-VIDEO LUMA 75 470pF 470pF 0.1µF 0.1µF 0.1µF COMPOSITE VIDEO Fig. 7. Recommended external component connections for NTSC 905 562 POWER FILTER AND + GND GND INVERTING 47 0.1µF AMPLIFIER VP536A/VP536B 13 VP536A/VP536B VP536A/VP536B PCB LAYOUT RECOMMENDATIONS To obtain the optimum performance from the Digital Signal Interconnect VP536A/VP536B video encoder, care must be taken in the The digital signal lines to the VP536A/VP536B should PCB layout to ensure low noise power and ground lines. This be isolated as much as possible from the analog circuitry. can be achieved by using power and ground planes, Due to the high clock rates used, the clock lines to the shielding the digital inputs and providing good decoupling. VP536A/VP536B should be as short as possible to minimize noise pickup. Power and Ground Planes Ideally, the VP536A/VP536B and its associated circuits Analog Signal Interconnect should have its own separate power and ground planes, For optimum performance, the analog video output which should be connected at a single point through a ferrite filters as well as the composite video inverting circuit should bead (such as Ferroxcude 5659065-3B, TDKBF45-4001 or be located as close as possible to the VP536A/VP536B to Fair-Rite 2743001111) to the regular PCB power and minimize noise pickup. The video output signals should ground. However, a separate analog power plane with a overlay the ground plane and not the analog power plane, to connection through a ferrite bead, along with a common maximize the high frequency power supply rejection. ground plane should be used as a minimum. It is important that the regular PCB power and ground planes do not overlay portions of the analog power or ground planes to minimize plane-to-plane noise coupling. Supply Decoupling Noise on the analog power plane will be further reduced by the use of multiple decoupling capacitor. Optimum performance is obtained with 0.1µF chip ceramic capacitors placed as close as possible to the VAA pins, with the shortest leads possible to reduce lead inductance. Connecting a similar 0.1µF capacitor between the LUMACOMP/CHROMACOMP and its neighboring VAA pins will help to improve high frequency power supply rejection. Ordering Information NTSC Only version: VP536A/CG/HPAS NTSC and PAL version: Contact your local sales office for availability. 14 VP536A/VP536B 15 VP536A/VP536B Package Details and Pin-Out All dimensions shown in mm/(inches) 0·66/0·81 PIN 1 PIN 68 PIN 1 PIN 1 REF. CORNER (0·026/0·032) REF. SIDE 0·508 (0·02) 1·14 (0·045) NOM. NOM. 345° 1·14 (0·045) NOM. 345° (0·944/0·964) (0·013/0·021) (0·985/0·995) 23·98/24·48 25·02/25·27 22·60/23·62 20·32 (0·80) OPTIONAL (0·89/0·93) 0·33/0·53 PIN 1 NOM. REFERENCE 68 LEADS AT 4·19/4·70 1·27 (0·050) (0·165/0·185) NOM. SPACING NOTES 1. Controlling dimensions are inches. 2. This package outline diagram is for guidance only. Please contact your GPS Customer Service Centre for further information. 68-LEAD QUAD PLASTIC J-LEAD – HP68 HEADQUARTERS OPERATIONS CUSTOMER SERVICE CENTRES GEC PLESSEY SEMICONDUCTORS • FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax : (1) 64 46 06 07 Cheney Manor, Swindon, • GERMANY Munich Tel: (089) 3609 06-0 Fax : (089) 3609 06-55 Wiltshire SN2 2QW, United Kingdom. • ITALY Milan Tel: (02) 33001044/45 Fax: (GR3) 316904 Tel: (0793) 518000 Tx: 449637 • JAPAN Tokyo Tel: (03) 3296-0281 Fax: (03) 3296-0228 Fax: (0793) 518411 • NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023. • SOUTH EAST ASIA Singapore Tel: 2919291 Fax: 2916455 GEC PLESSEY SEMICONDUCTORS • SWEDEN Johanneshov Tel: 46 8 7228690 Fax: 46 8 7227879 P.O.Box 660017 • UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (0793) 518510 Fax: (0793) 518582 1500 Gren Hills Road, Scotts Valley, California 95067-0017, These are supported by Agents and Distributors in major countries world-wide. United States of Amercia. Tel: (408) 438 2900 © GEC Plessey Semiconductors 1994Publication No. DS3925Issue No. 2.1 September 1994 Fax: (408) 438 5576 This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.