This file is raw output from pdftotext and may not be ideal for distribution. If you are a maintainer for Hackipedia, please sit down when you have time and clean this text version up. Source PDF: /mnt/fw-js/docs/Hardware/RAM, volatile computer memory/pdf, Toshiba/TOSHIBA SILICON GATE CMOS TC528267 262,144WORDS x 8BITS MULTIPORT DRAM.pdf Like all conversions the text below should be fully readable as UTF-8 unicode text. --------------------------------------------------------------- TOSHIBA SILICON GATE CMOS TC528267 t a r g e t s p e c 262,144WORDS x 8BITS MULTIPORT DRAM DESCRIPTION The TC528267 is a 2M bit CMOS multiport memory equipped with a 262,144-words by 8-bits dynamic random access memory (RAM) port and a 512-words by 8-bits static serial access memory (SAM) port. The TC528267 supports three types of operations; Random access to and from the RAM port, high speed serial access to and from the SAM port and bidirectional transfer of data between any selected row in the RAM and the SAM. To realize a high performance graphic frame buffer system the TC528267 features various special operations such as the write - per - bit, the pipelined page mode, the block write and flash write function on the RAM port and the read and masked write transfer operations between the RAM and the SAM port. In addition, the TC528267 is fabricated using Toshiba's CMOS silicon gate process as well as advanced circuit designs to provide low power dissipation and wide operating margins. FEATURES KEY PARAMETERS • Single power supply of 5 V± 10% with a built-in VBB generator ITEM • All inputs and outputs : TTL Compatible — 70 — 80 • Organization tRAC RAS Access Time RAM Port : 262,l44wordsX8bits 70ns 80ns (Max.) SAM Port : 5l2wordsX8bits tCAC CAS Access Time • RAM Port 20ns 20ns (Max.) Extended Fast Page Mode, Read - Modify - Write, Pipelined Fast Page Mode, CAS before tAA Column Address Access 35ns 40ns RAS Auto Refresh, Hidden Refresh, RAS only Time (Max.) Refresh, Write per Bit (New/Old Mask Mode), tRC Cycle Time (Min.) l30ns l50ns Masked Flash Write (New/Old Mask Mode), tPC Page Mode Cycle Time Block Write, Masked Block Write (New/Old 35ns 40ns (Min.) Mask Mode), Load Mask Register/Color Register Cycle, 512 refresh cycles / 8ms tSCA Serial Access Time 20ns 25ns (Max.) • SAM Port Serial Read / Write Capability tSCC Serial Cycle time (Min.) 25ns 30ns Addressable TAP Capability tRACP tRAC in Pipelined Fast Stop Address (Binary Boundary) Capability 90ns 95ns Page Fully Static Register, SIngle Register/Split Register Mode Capability tCAC1 tCAC in Pipelined Fast 20ns 20ns Page • RAM - SAM Bidirectional Transfer Read / Real Time Read Transfer tPCP Pipelined Fast Page 30ns 30ns Masked Write Transfer Mode Cycle Time Split Read / Masked Split Write Transfer ICC1 RAM Operating Current 100mA 85mA • Package (SAM : Standby) TC528267J : SOJ40-P-400 ICC2A SAM Operating Current TC528267FT : TSOP44-P-400B 60mA 50mA (RAM : Standby) TC528267TR : TSOP44-P-400C I CC2 Standby Current l0mA l0mA 1/62 TOSHIBA CORPORATION TC528267 PIN NAME A0~A8 Address inputs RAS Row Address Strobe CAS Column Address Strobe DT/OE Data Transfer/Output Enable WB/WE Write per Bit/Write Enable DSF1 Special Function Control DSF2 W1/IO1~W8/IO8 Write Mask/Data IN OUT SC Serial Clock SE Serial Enable SIO1~SIO8 Serial Input/Output QSF Special Flag Output VCC/VSS Power (5V)/Ground N.C. No Connection PIN CONNECTION (TOP VIEW) 2/62 TOSHIBA CORPORATION TC528267 BLOCK DIAGRAM 3/62 TOSHIBA CORPORATION TC528267 ABSOLUTE MAXIMUM RATINGS SYMBOL lTEM RATING UNIT NOTE VIN, VOUT Input Output Voltage — 1.0~7.0 V 1 VCC Power Supply Voltage — I .0~7.0 V 1 TOPR Operating Temperature 0~70 °C 1 TSTG Storage Temperature — 55~150 °C 1 TSOLDER Soldering Temperature • Time 260•10 °C•sec 1 PD Power Dissipation 1 W 1 IOUT Short Circuit Output Current 50 mA 1 RECOMMENDED D.C. OPERATING CONDITIONS (Ta = 0~70°C) SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTE VCC Power Supply Voltage 4.5 5.0 5.5 V 2 VIH Input High Voltage 2.4 — 6.5 V 2 VIL Input Low Voltage - 1.0 — 0.8 V 2 +: -1V 20ns Pulse width CAPACITANCE (VCC = 5V, f = 1MHz, Ta = 25°C) SYMBOL PARAMETER MIN. MAX. UNIT C Input Capacitance — 7 I C Input/Output Capacitance — 9 IO pF CO Output Capacitance (QSF) — 9 Note: This parameter is periodically sampled and is not 100% tested. 4/62 TOSHIBA CORPORATION TC528267 D.C. ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, Ta = 0~70°C) -70 -80 ITEM (RAM PORT) SAM PORT SYMBOL UNIT NOTE MIN. MAX. MIN. MAX. OPERATING CURRENT Standby ICC1 — 100 — 90 3, 4, 5 RAS, CAS Cycling tRC = tRC min. Active ICC1A — 160 140 3, 4, 5 STANDBY CURRENT Standby ICC2 — 10 — 10 RAS, CAS = VIH Active ICC2A — 65 — 55 3, 4, 5 RAS ONLY REFRESH CURRENT Standby ICC3 — 100 — 90 3, 4 RAS Cycling, CAS = VIH tRC = tRC min. Active ICC3A — 160 — 140 3, 4, 5 PAGE MODE CURRENT Standby ICC4 — 90 — 80 3, 4, 5 RAS = VIL, CAS Cycling tPC = tPC min. Active ICC4A — 150 — 130 3, 4, 5 mA CAS BEFORE RAS REFRESH CURRENT Standby ICC5 — 100 — 90 3, 4, 5 RAS Cycling, CAS Before RAS tRC = tRC min. Active ICC5A — 160 — 140 3, 4, 5 DATA TRANSFER CURRENT Standby ICC6 — 135 — 125 3, 4, 5 RAS, CAS Cycling tRC = tRC min. Active ICC6A — 195 — 175 3, 4, 5 FLASH WRITE CURRENT Standby ICC7 — 100 — 90 3, 4, 5 RAS, CAS Cycling tRC = tRC min. Active ICC7A — 160 — 140 3, 4, 5 BLOCK WRITE CURRENT Standby ICC8 — 110 — 100 3, 4, 5 RAS, CAS Cycling tRC = tRC min. Active ICC8A — 170 — 150 3, 4, 5 ITEM SYMBOL MIN. MAX UNIT NOTE INPUT LEAKAGE CURRENT II(L) —10 10 µA 0V ≤ VIN ≤ 6.5V, All other pins not under test=0V OUTPUT LEAKAGE CURRENT IO(L) —10 10 µA 0V ≤ VOUT ≤ 5.5V, OutputDisable OUTPUT “H” LEVEL VOLTAGE VOH 2.4 — V IOUT = - 1mA OUTPUT “L” LEVEL VOLTAGE VOL — 0.4 V IOUT = 2.1mA 5/62 TOSHIBA CORPORATION TC528267 ELECTRICAL CHARACTERISTICS AND RECOMMENDED A.C. OPERATING CONDITIONS (VCC = 5V ± 10%, Ta = 0~70°C)(Notes: 6, 7, 8) -70 -80 SYMBOL PARAMETER UNIT NOTE MIN. MAX. MIN. MAX. tRC Random Read or Write Cycle Time 130 150 tRMW Read-Modify-Write Cycle Time 180 200 tPC Fast Page Mode Cycle Time 35 40 tPRMW Fast Page Mode Read-Modify-Write CycleTime 90 90 tRAC Access Time from RAS 70 80 9, 15 tAA Access Time from Column Address 35 40 9, 15 tCAC Access Time from CAS 20 20 9, 16 tCPA Access Time from CAS Precharge 35 40 9, 16 tCLZ CAS to Output in Low-Z 0 0 tOELZ OE to Output in Low-Z 0 0 tOFF Output Buffer Turn-Off Delay 0 15 0 15 11, 17 tT Transition Time (Rise and Fall) 3 50 3 50 8 tRP RAS Precharge Time 50 60 tRAS RAS Pulse Width 70 10000 80 10000 tFASP RAS Pulse Width (Fast Page Mode Only) 70 100000 80 100000 tRSH RAS Hold Time 20 20 tCSH CAS Hold Time 70 80 tCAS CAS Pulse Width 15 10000 20 10000 tRCD RAS to CAS Delay Time 20 50 20 60 15 tRAD RAS to Column Address Delay Time 15 35 15 40 15 tRAL Column Address to RAS Lead Time 35 40 tCRP CAS to RAS Precharge Time 5 5 tCPN CAS Precharge Time 10 10 ns tCP CAS Precharge Time (Fast Page Mode) 10 10 tASR Row Address Set-Up Time 0 0 tRAH Row Address Hold Time 10 10 tASC Column Address Set-Up Time 0 0 tCAH Column Address Hold Time 12 15 tRCS Read Command Set-Up Time 0 0 tRCH Read Command Hold Time 0 0 12 tRRH Read Command Hold Time referenced to RAS 0 0 12 tWCH Write Command Hold Time 10 15 tWP Write Command Pulse Width 10 10 tWPZ Write Command Pulse Width 10 15 11 tWEZ Write Command Output Buffer Turn-Off Delay 10 15 11 tRWL Write Command to RAS Lead Time 20 20 tCWL Write Command to CAS Lead Time 15 20 tDS Data Set-Up Time 0 0 13 tDH Data Hold Time 12 15 13 tWCS Write Command Set-Up Time 0 0 14 tRWD RAS to WE Delay Time 95 105 14 tAWD Column Address to WE Delay Time 60 65 14 tCWD CAS to WE Delay Time 45 45 14 tCOH CAS Hold TIme referenced to OE 5 5 tRES RAS to SC boundary - reset Time 30 30 6/62 TOSHIBA CORPORATION TC528267 -70 -80 SYMBOL PARAMETER UNIT NOTE MIN. MAX MIN. MAX. tDZC Data to CAS Delay Time 0 0 tDZO Data to OE Delay Time 0 0 tOEA Access Time from OE 20 20 9 tOEZ Output Buffer Turn-off Delay from OE 15 15 11 tOED OE to Data Delay Time 15 15 tOEH OE Command Hold Time 15 15 ns tODS Output Disable Set up time 0 0 tROH RAS Hold Time referenced to OE 15 15 tCSR CAS Set-Up Time for CAS Before RAS Cycle 5 5 tCHR CAS Hold Time for CAS Before RAS Cycle 10 15 tRPC RAS Precharge to CAS Active Time 0 0 tREF Refresh Period 8 8 ms tWSR WB Set-Up Time 0 0 tRWH WB Hold Time 10 15 tFSR DSF Set-Up Time referenced to RAS 0 0 tRFH DSF Hold Time referenced to RAS(1) 10 15 tFSC DSF Set-Up Time referenced to CAS 0 0 tCFH DSF Hold Time referenced to CAS 12 15 tMS Write-Per-Bit Mask Data Set-Up Time 0 0 tMH Write-Per-Bit Mask Data Hold Time 10 15 tTHS DT High Set-Up Time 0 0 tTHH DT High Hold Time 10 15 tTLS DT Low Set-Up Time 0 0 tTLH DT Low Hold Time 10 10000 15 10000 tRTH DT Low Hold Time referenced to RAS 60 65 (Real Time Read Transfer) 10000 10000 ns tATH DT Low Hold Time referenced to Column 25 25 Address (Real Time Read Transfer) tCTH DT Low Hold Time referenced to CAS 20 20 (Real Time Read Transfer) tTRP DT to RAS Precharge Time 50 60 tTP DT Precharge Time 15 15 tRSD RAS to First SC Delay Time (Read Transfer) 70 80 tASD Column Address to First SC Delay Time 35 40 (Read Transfer) tCSD CAS to First SC Delay Time (Read Transfer) 20 20 tTSL Last SC to DT Lead Time (Real Time Read Transfer) 5 5 tTSD DT to FIrst SC Delay Time (Read Transfer) 10 15 tSRS Last SC to RAS Set-Up Time (Serial Input) 25 30 tSRD RAS to First SC Delay Time (Serial Input) 20 25 tSDD RAS to Serial Input Delay Time 45 50 7/62 TOSHIBA CORPORATION TC528267 -70 -80 SYMBOL PARAMETER UNIT NOTE MIN. MAX. MIN. MAX. tSCC SC Cycle Time 25 30 tSC SC Pulse Width (SC High Time) 10 10 tSCP SC Precharge Time (SC Low Time) 5 10 tSCA Access Time from SC 20 25 10 tSOH Serial Output Hold Time from SC 5 5 tSDS Serial Input Set-Up Time 0 0 tSDH Serial Input Hold Time 10 15 tSEA Access Time from SE 20 25 10 tSE SE Pulse Width 20 25 tSEP SE Precharge Time 20 25 tSEZ Serial Output Buffer Turn-off Delay from SE 15 20 11 tSZE Serial to SE Delay Time 0 0 tSZS Serial Input to First SC Delay Time 0 0 tSWS Serial Write Enable Set-Up Time 0 0 tSWH Serial Write Enable Hold Time 10 15 tSWIS Serial Write Disable Set-Up Time 0 0 tSWIH Serial Write Disable Hold Time 10 10 tSTS Split Transfer Set-Up Time 25 30 tSTH Split Transfer Hold Time 25 30 ns tSAAT Split Transfer SC Set-Up Time from RAS 45 55 tSAA Split Transfer SC Hold Time from RAS 0 0 tSQD SC-QSF Delay Time 20 25 tTQD DT-QSF Delay Time 20 25 tCQD CAS-QSF Delay Time 20 25 tRQD RAS-QSF Delay Time 70 80 tRCDP RAS to CAS Delay Time (Pipeline mode) 20 40 20 45 tCSHP CAS Hold Time (Pipeline mode) 50 55 tRACP Access TIme from RAS (Pipeline mode) 90 95 tCAC1 Access Time from CAS (1) (Pipeline mode) 20 20 10 tCAC2 Access Time From CAS (2) (Pipeline mode) 50 50 10 tCASP CAS Pulse Width (Pipeline mode) 10 10 tCPP CAS Precharge Time Pipeline mode) 10 10 tPCP Fast Page Mode Cycle Time (Pipeline mode) 30 30 tRSH1 RAS Hold Time (1) (Pipeline mode) 20 20 tRSH2 RAS Hold Time (2) (Pipeline mode) 50 50 tCWLP Write Command to CAS lead Time (Pipeline mode) 10 10 tCWP WE to CAS Delay Time (Pipeline mode) 30 30 tOFFP Outoff Buffer Turn-off Delay from RAS (Pipeline mode) 0 15 0 15 11, 17 RAM Output Reference Level 2.0V/0.8V SAM Output Reference Level 2.0V/0.8V RAM Output Load 1 TTL and 50PF SAM Output Load 1 TTL and 30PF 8/62 TOSHIBA CORPORATION TC528267 NOTES: 01. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. 02. All voltage are referenced to VSS. 03. These parameters depend on cycle rate. 04. These parameters depend on output loading. Specified values are obtained with the output open. 05. Address can be changed once or less while RAS=VIL. In case of ICC4, it can be changed once or less during a fast page mode cycle (tPC). 06. An initial pause of 200 µs is required after power-up followed by any 8 CAS before RAS initialisation cycles before proper device operation is achieved. 07. AC measurements assume tT = 5ns. 08. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 09. RAM port outputs are measured with a load equivalent to 1 TTL load and 50pF. DOUT reference levels : VOH / VOL = 2.0V / 0.8V. 10. SAM port outputs are measured with a load equivalent to 1 TTL load and 30pF. DOUT reference levels : VOH / VOL = 2.0V / 0.8V. 11. tOFF (max.), tOEZ (max.), tOFFP (max.),tWPZ (max.), tWEZ (max.), and tSEZ (max.) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. These parameters are referenced to CAS leading edge of early write cycles and to WB / WE leading edge in OE-controlled-write cycle and read-modify-write cycles. 14. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (min.), the cycle is an early write cycles and the data out pin will remain open circuit (high impedance) throughout the entire cycle; If tRWD ≥ tRWD (min.), tCWD ≥ tCWD (min.) and tAWD ≥ tAWD (min.) the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell : If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only : If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 16. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 17. tOFF, tOFFP timing is specified from either RAS or CAS rising edge, whichever occurs last. 9/62 TOSHIBA CORPORATION TC528267 TIMING WAVEFORM READ CYCLE 10/62 TOSHIBA CORPORATION TC528267 WRITE CYCLE (EARLY WRITE) Mask Mode *1 *2 Cycle No Mask Mode 1 Don’t care Normal Write New Mask Mode 0 WM1 data Write per Bit Old Mask Mode 0 Don’t care Write per Bit WM1 data 0: Write Disable 1: Write Enable Don’t care 0: ‘1’ or ‘0’ 11/62 TOSHIBA CORPORATION TC528267 WRITE CYCLE (OE CONTROLLED WRITE) Mask Mode *1 *2 Cycle No Mask Mode 1 Don’t care Normal Write New Mask Mode 0 WM1 data Write per Bit Old Mask Mode 0 Don’t care Write per Bit WM1 data 0: Write Disable 1: Write Enable Don’t care 0: ‘1’ or ‘0’ 12/62 TOSHIBA CORPORATION TC528267 READ-MODIFY-WRITE CYCLE Mask Mode *1 *2 Cycle No Mask Mode 1 Don’t care Normal Write New Mask Mode 0 WM1 data Write per Bit Old Mask Mode 0 Don’t care Write per Bit WM1 data 0: Write Disable 1: Write Enable Don’t care 0: ‘1’ or ‘0’ 13/62 TOSHIBA CORPORATION TC528267 EXTENDED FAST PAGE MODE READ CYCLE 14/62 TOSHIBA CORPORATION TC528267 EXTENDED FAST PAGE MODE WRITE CYCLE (EARLY WRITE) Mask Mode *1 *2 Cycle No Mask Mode 1 Don’t care Normal Write New Mask Mode 0 WM1 data Write per Bit Old Mask Mode 0 Don’t care Write per Bit WM1 data 0: Write Disable 1: Write Enable Don’t care 0: ‘1’ or ‘0’ 15/62 TOSHIBA CORPORATION TC528267 EXTENDED FAST PAGE MODE READ-MODIFY-WRITE CYCLE Mask Mode *1 *2 Cycle No Mask Mode 1 Don’t care Normal Write New Mask Mode 0 WM1 data Write per Bit Old Mask Mode 0 Don’t care Write per Bit WM1 data 0: Write Disable 1: Write Enable Don’t care 0: ‘1’ or ‘0’ 16/62 TOSHIBA CORPORATION TC528267 FLASH WRITE CYCLE Mask Mode *1 New Mask Mode WM1 data Old Mask Mode Don’t care WM1 data 0: Flash Write Disable 1: Flash Write Enable Don’t care 0: ‘0’ or ‘1’ 17/62 TOSHIBA CORPORATION TC528267 BLOCK WRITE CYCLE (EARLY WRITE) Mask Mode *1 *2 *3 COLUMN SELECT } No Mask Mode 1 Don’t care W1/IO1 - Column 0 (A1C=0, A0C=0 Wn/IOn W2/IO2 - Column 1 (A1C=0, A0C=1 =0 : Disable New Mask Mode 0 WM1 data W3/IO3 - Column 2 (A1C=1, A0C=0 =1 : Enable W4/IO4 - Column 3 (A1C=1, A0C=1 Old Mask Mode 0 Don’t care WM1 data 0: Write Disable 1: Write Enable Don’t care 0: ‘0’ or ‘1’ 18/62 TOSHIBA CORPORATION TC528267 BLOCK WRITE CYCLE (DELAYED WRITE) Mask Mode *1 *2 *3 COLUMN SELECT } W1/IO1 - Column 0 (A1C=0, A0C=0 Wn/IOn No Mask Mode 1 Don’t care W2/IO2 - Column 1 (A1C=0, A0C=1 =0 : Disable W3/IO3 - Column 2 (A1C=1, A0C=0 =1 : Enable New Mask Mode 0 WM1 data W4/IO4 - Column 3 (A1C=1, A0C=1 Old Mask Mode 0 Don’t care WM1 data 0: Write Disable 1: Write Enable Don’t care 0: ‘0’ or ‘1’ 19/62 TOSHIBA CORPORATION TC528267 FAST PAGE MODE BLOCK WRITE CYCLE Mask Mode *1 *2 *3 COLUMN SELECT } W1/IO1 - Column 0 (A1C=0, A0C=0 No Mask Mode 1 Don’t care Wn/IOn W2/IO2 - Column1 (A1C=0, A0C=1 =0 : Disable W3/IO3 - Column 2 (A1C=1, A0C=0 New Mask Mode 0 WM1 data =1 : Enable W4/IO4 - Column 3 (A1C=1, A0C=1 Old Mask Mode 0 Don’t care WM1 data 0: Write Disable 1: Write Enable Don’t care 0: ‘0’ or ‘1’ 20/62 TOSHIBA CORPORATION TC528267 RAS ONLY REFRESH CYCLE 21/62 TOSHIBA CORPORATION TC528267 HIDDEN REFRESH CYCLE 22/62 TOSHIBA CORPORATION TC528267 CBR AUTO REFRESH CYCLE 23/62 TOSHIBA CORPORATION TC528267 CBR AUTO REFRESH & STOP REGISTER SET CYCLE 24/62 TOSHIBA CORPORATION TC528267 CBR AUTO REFRESH & RESET CYCLE 25/62 TOSHIBA CORPORATION TC528267 LOAD MASK/COLOR REGISTER CYCLE *1 *2 Function 0 Mask data Load Mask Register Cycle 1 Color data Load Color Register Cycle 26/62 TOSHIBA CORPORATION TC528267 READ MASK/COLOR REGISTER CYCLE *1 *2 Function 0 Mask data Read Mask Register Cycle 1 Color data Read Color Register Cycle 27/62 TOSHIBA CORPORATION TC528267 PIPELINED FAST PAGE READ CYCLE 28/62 TOSHIBA CORPORATION TC528267 PIPELINED FAST PAGE WRITE CYCLE Mask Mode *1 *2 Cycle No Mask Mode 1 Don’t care Normal Write New Mask Mode 0 WM1 data Write per Bit Old Mask Mode 0 Don’t care Write per Bit WM1 data 0: Write Disable 1: Write Enable Don’t care 0: ‘1’ or ‘0’ 29/62 TOSHIBA CORPORATION TC528267 PIPELINED FAST PAGE READ-WRITE CYCLE Mask Mode *1 *2 Cycle No Mask Mode 1 Don’t care Normal Write New Mask Mode 0 WM1 data Write per Bit Old Mask Mode 0 Don’t care Write per Bit WM1 data 0: Write Disable 1: Write Enable Don’t care 0: ‘1’ or ‘0’ 30/62 TOSHIBA CORPORATION TC528267 PIPELINED FAST PAGE WRITE-READ CYCLE Mask Mode *1 *2 Cycle No Mask Mode 1 Don’t care Normal Write New Mask Mode 0 WM1 data Write per Bit Old Mask Mode 0 Don’t care Write per Bit WM1 data 0: Write Disable 1: Write Enable Don’t care 0: ‘1’ or ‘0’ 31/62 TOSHIBA CORPORATION TC528267 PIPELINED FAST PAGE WRITE-BLOCK WRITE CYCLE Mask Mode *1 *2 Cycle No Mask Mode 1 Don’t care Normal Write New Mask Mode 0 WM1 data Write per Bit Old Mask Mode 0 Don’t care Write per Bit WM1 data 0: Write Disable 1: Write Enable Don’t care 0: ‘1’ or ‘0’ 32/62 TOSHIBA CORPORATION TC528267 READ TRANSFER CYCLE (Previous Transfer is Write Transfer Cycle) 33/62 TOSHIBA CORPORATION TC528267 REAL TIME READ TRANSFER CYCLE 34/62 TOSHIBA CORPORATION TC528267 SPLIT READ TRANSFER CYCLE 35/62 TOSHIBA CORPORATION TC528267 MASKED WRITE TRANSFER CYCLE Mask Mode *1 New Mask Mode WM1 data Old Mask Mode Don’t care WM1 data 0: Transfer Disable 1: Transfer Enable Don’t care 0: ‘0’ or ‘1’ 36/62 TOSHIBA CORPORATION TC528267 MASKED WRITE TRANSFER CYCLE (Previous Transfer is Read Transfer Cycle) Mask Mode *1 New Mask Mode WM1 data Old Mask Mode Don’t care WM1 data 0: Transfer Disable 1: Transfer Enable Don’t care 0: ‘0’ or ‘1’ 37/62 TOSHIBA CORPORATION TC528267 MASKED SPLIT WRITE TRANSFER CYCLE Mask Mode *1 New Mask Mode WM1 data Old Mask Mode Don’t care WM1 data 0: Transfer Disable 1: Transfer Enable Don’t care 0: ‘0’ or ‘1’ 38/62 TOSHIBA CORPORATION TC528267 SERIAL READ CYCLE (SE = VIL) SERIAL READ CYCLE (SE Controlled Outputs) 39/62 TOSHIBA CORPORATION TC528267 SERIAL WRITE CYCLE (SE = VIL) SERIAL WRITE CYCLE (SE Controlled Inputs) PIN FUNCTION ADDRESS INPUTS : A0~A8 The 18 address bits are required to decode 8 bits of the 2,097,152 cell locations within the dynamic RAM memory array and they are multiplexed onto 9 address input pins (A0~A8). Nine row address bits are latched on the falling edge of the row address strobe (RAS) and the following nine column address bits are latched on the falling edge of the column address strobe (CAS). 40/62 TOSHIBA CORPORATION TC528267 ROW ADDRESS STROBE : RAS A random access cycle or a data transfer cycle begins at the falling edge of RAS. RAS is the control input that latches the row address bits and the states of CAS, DT/OE, WB/WE, DSF1 and DSF2 to invoke the various random access and data transfer operating modes shown in Table 1. RAS has minimum and maximum pulse widths and a minimum precharge requirement which must be maintained for proper device operation and data integrity. The RAM port is placed in standby mode when the RAS control is held “high”. COLUMN ADDRESS STROBE : CAS CAS is the control input that latches the column address bits which are also used for the tap address during the transfer operations. The state of the special function input DSF1 is read at the CAS falling edge to select the block write mode or load register functions in conjunction with the RAS control. CAS before RAS refresh operations are selected if the signal is “low” at the RAS falling edge. DATA TRANSFER/OUTPUT ENABLE : DT/OE The DT/OE input is a multifunction pin. When DT/OE is “high” at the falling edge of RAS, RAM port operations are performed and DT/OE is used as an output enable control. If it is “low”, a data transfer operation is activated between the RAM and the SAM. 41/62 TOSHIBA CORPORATION TC528267 WRITE PER BIT/WRITE ENABLE : WB/WE The WB/WE input is also a multifunction pin. When the signal is “high” at the falling edge of RAS, during the RAM port operations, it is used to write data into the memory array in the same manner as a standard DRAM. If the signal is “low” at the RAS falling edge, the write-per-bit function is enabled. The WB/WE input also determines the direction of data transfer between the RAM array and the SAM. WRITE MASK DATA/DATA INPUT AND OUTPUT: W1 /IO1~W8/IO8 Data is written into the RAM through W1/IO1~W8/IO8 pins during a write cycle. The input data is latched at the falling edge of either CAS or WB/WE, whichever occurs late. In a read cycle data is read out of the RAM on the Wi / IOi pins after the specified access times from RAS, CAS, DT/OE and column address. The 4 least bits are also used as the column address mask during a block write cycle. When the write-per-bit function is enabled, the mask data on the Wi/IOi pins is latched into the write mask register at the falling edge of RAS. In a load mask and color register cycles, the data on the Wi/IOi pins is stored into the write mask register and the color register respectively. SERIAL CLOCK : SC All operations of the SAM port are synchronized with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. The serial clock SC also increments the 9-bits serial pointer which is used to select the SAM address. The SC pin must be held at a constant VIH or VIL level during read and masked write transfer operations and should not be clocked while the SAM is in standby mode to prevent the SAM pointer from being incremented. 42/62 TOSHIBA CORPORATION TC528267 SERIAL ENABLE : SE The SE input is used to enable serial access operation. In a serial read cycle, SE is used as an output control. In a serial write cycle, SE is used as a write enable control. When SE is “high”, serial access is disabled, however, the serial address pointer is still incremented while SC is clocked. SPECIAL FUNCTION CONTROL INPUT: DSF1, DSF2 DSF1 is latched at the falling edge of RAS and CAS to select the various TC528267 operations. If the signal is kept “low”, the basical functions featured in conventional multi-port DRAM are enabled. To use the block write, the flash write and the load register functions or the split transfer operations, the DSF1 signal needs to be controlled as shown in Table 1. When the DSF2 signal is “high” at the falling edge of RAS, pipelined page mode operations are enabled. The pipeline mode is supported with the read, write and block write functions. SPECIAL FUNCTION OUTPUT: QSF QSF is an output signal which, during split register mode, indicates which half of the split SAM is being accessed. QSF “low” indicates that the lower split SAM (Bit 0~255) is being accessed and QSF “high” indicates that the upper split SAM (Bit 256~511) is being accessed. QSF is monitored so that after it toggles and after allowing for a delay of tSTS, split read/write transfer operation can be performed on the non-active split SAM. SERIAL INPUT/OUTPUT : SIO1~SIO8 Serial input and serial output share common I/O pins. Serial input or output mode is determined by the most recent read or masked write transfer cycle. After a read cycle, the SI/Oi pin is in the output mode. When a masked write transfer cycle is performed, the SI/Oi is switched from output mode to input mode, OPERATION MODE The RAM port and data transfer operating of the TG528267 are determined by the state of CAS, DT/OE, WB/WE, DSF1 and DSF2 at the falling edge of RAS and by the state of DSF1 at the falling edge of CAS. The Table 1 shows the functional truth table for a listing of all available RAM port and transfer operations. 43/62 TOSHIBA CORPORATION TC528267 Table 1. Functional Truth Table RAS CAS Mnemonic Code Function CAS DT/OE WB/WE DSF1 DSF2 DSF1 0 * * 0 * - CBR CBR Auto Refresh & Option Reset 1), 2) 0 * 0 1 * - CBRS CBR Auto Refresh & Stop Register 2) 0 * 1 1 * - CBRN CBR Auto Refresh 1 0 0 0 * * MWT Write Transer (New/Old Mask)1) 1 0 0 1 * * MSWT Split Write Transfer (New/Old Mask)1) 1 0 1 0 * * RT Read Transfer 1 0 1 1 * * SRT Split Read Transfer 1 1 0 0 0 0 RWM Read Write (New/Old Mask)1) 1 1 0 0 0 1 BWM Block Write (New/Old Mask)1) 1 1 0 1 * * FWM Flash Write (New/Old Mask)1) Read Write with Extended Fast Page 1 1 1 0 0 0 RW Mode (No Mask) 1 1 1 0 0 1 BW Block Write (No Mask) 1 1 0 0 1 0 RWM(P) PFP3) Read Write (New/Old Mask)1) 1 1 0 0 1 1 BWM(P) PFP3) Block Write (New/Old Mask)1) 1 1 1 0 1 0 RW(P) PFP3) Read Write (No Mask) 1 1 1 0 1 1 BW(P) PFP3) Block Write (No Mask) 1 1 1 1 * 0 LMR Load (Old) Mask Register1) 1 1 1 1 * 1 LCR Load Color Register Note : * =0 or 1, - = Not applicable 1) After LMR operation, MWT, MSWT, RWM, BWM, FWM, RWM (P), BWM (P) use old mask. CBR operation resets the old mask mode to new mask mode. 2) CBRS operation determines binary boundaries in the SAM. CBR operation resets the boundaries. 3) PFP stands for pipelined fast page mode RAM PORT OPERATION 1. READ WRITE FUNCTION : RW The TC528267 is equipped with the read write function which is identical to the conventional dynamic RAM's one and supports read, early write, OE controlled write and read-modify-write cycles as shown in the timing charts. Extended fast page and pipelined page modes are also available with the read write cycles by performing multiple CAS cycles during a single active RAS cycle, a page. 44/62 TOSHIBA CORPORATION TC528267 1.1 EXTENDED FAST PAGE MODE Extended fast page mode allows faster access to the memory in an actual system than the conventional fast page mode. An output data remains valid after the CAS signal goes high to prepare the next output data. Thus, the system has longer period to read the data from the RAM. Read, write and read-modify-write cycles are available during the extended fast page mode. 2. WRITE-PER-BIT (MASKED WRITE) FUNCTION : RWM The write-per-bit (masked write) function selectively controls the internal write enable circuits of the RAM port. When WB/WE is held “low” at the falling edge of RAS, during the RWM cycle, the write mask is enabled. At the same time, the mask data on the Wi/IOi pins is latched into the write-mask register. The I/O mask data maintains in a single RAS cycle, a page (New Mask Mode). When a load mask register function (LMR) is performed, the write mask data on the Wi/IOi pins is latched into the write-mask register. After the LMR operation, the data at the falling edge of RAS during the RWM cycle is ignored and the I/O mask data that was stored in the write-mask register is used (Old Mask Mode) until the mode is reset by CBR operation. The truth table of the write-per-bit function is shown in Table 2. Table 2. Truth table for write-per-bit function At the falling edge of RAS Write Mask Register Function CAS DT/OE WB/WE Wi/IOi (i=1~8) 1 ← Write Enable 0 ← Write Disable (New Mask) H H L * 1 Write Enable * 0 Write Disable (Old Mask) Note:* = 1 or 0 , ← = The data on Wi/IOi is latched. 3. BLOCK WRITE AND MASKED BLOCK WRITE : BW & BWM Block write is a special RAM port write operation which, in a page, allows for the data in the color register to be written into 4 consecutive column address locations starting from a selected column address in a selected row. The block write operation can be selectively disabled on an I/O basis and a column mask capability is also available. 45/62 TOSHIBA CORPORATION TC528267 A block write cycle is performed by holding CAS, DT/OE “high” and DSF1 “low” at the RAS falling edge and by holding DSF1 “high” at the CAS falling edge. If the DSF signal is “low” at the CAS falling edge, a read write operation will occur. Therefore, a combination of block write, read and write operations can be performed during a fast page mode cycle. The state of WB/WE input at the falling edge of RAS determines whether or not the I/O mask is enabled (WB/WE must be “low” to enable the I/O mask, BMW mode or “high” to disable it, BW mode). The I/O mask is provided on the Wi/IOi input at the RAS falling edge. After LMR operation, however, the old mask is used for the I/O mask function. The column mask data on the Wi/IOi input must be provided at the CAS or WB/WE falling edge whichever is late, while the seven most significant colunm address (A2C~A8C) are latched at the falling edge of CAS. An example of the block write function is shown in Figure 1 with a mask on W3/IO3, W4/IO4, W6/IO6, W8/IO8 and column 1. The block write is most effective for window clear and fill operation in frame buffer applications. Figure 1. Block Write Operation *1 *2 Mask Mode *3 COLUMN SELECT 1 Don’t Care No Mask Mode W1/IO1 - Column 0 (A1C=0, A0C=0 W2/IO2 - Column 1 (A1C=0, A0C=1 0 WM1 New Mask Mode W3/IO3 - Column 2 (A1C=1, A0C=0 W4/IO4 - Column 3 (A1C=1, A0C=1 0 Don’t Care Old Mask Mode 46/62 TOSHIBA CORPORATION TC528267 4. FLASH WRITE : FWM Flash write is also a special RAM port operation which in a single RAS cycle, allows for the data in the color register to be written into all the memory locations of a selected row. Each bit of the color register corresponds to one of the DRAM I/O blocks and the flash write operation can be selectively controlled on an I/ O basis in the same manner as the write-per-bit operation. A flash write cycle is performed by holding CAS “high”, WB/WE “low” and DSF1 “high” at the falling edge of RAS. The mask data must also be provided on the Wi/IOi inputs in order to enable the flash write operation for selected I/O blocks. After a LMR operation, however, the old mask in the mask register is used for the I/O block masking. Flash write is most effective for fast plane clear operations in frame buffer applications. Selected planes can be cleared by performing 512 flash write cycle and by specifying a different row address location during each flash write cycle. Assuming a cycle time of 130ns, a plane clear operation can be completed in less than 66.6 µsec. Figure 2. Flash Write Operation * Mask Mode Mask Data New Mask Mode Don't Care (H or L) Old Mask Mode 47/62 TOSHIBA CORPORATION TC528267 5. PIPELINED FAST PAGE MODE : RWM (P), BWM (P), RW (P), BW (P) Pipelined fast page mode allows much faster access to the memory than the conventional page mode. Read, write and block write cycles are available at the pipelined fast page mode timings. A pipelined fast page mode is performed by holding DSF2 “high” at the falling edge of RAS. A pipelined fast page read, write and block write operations can run at 30ns cycle time for 70ns version. Also, those mode can be selected every CAS cycle by the status of DT/OE, WB/WE and DSF1 pin. There are, however, penalties on the performance as follows : (1) Two CAS cycles are required for the read operation. The fast access, hence, takes longer than page mode. Also, one CAS cycle is needed to read out the data before the write cycle starts in the same page. (2) One dummy cycle is needed to complete the write and block write operation. The cycle is, thus, needed between the write and the read operation and is required before the page ends. A system designer needs to carefully estimate the system performances with the pipelined page mode and the conventional page mode in order to decide which mode should be used. 6. LOAD (OLD) MASK REGISTER : LMR The TC528267 has an on-chip 8 bit write-mask register which provides the I/O mask data during the masked functions such as the write-per-bit (RWM), masked block write (BWM), flash write (FWM) and write transfer (MWT, MSWT) functions. Each bit of the write-mask register corresponds to one of the DRAM I/O blocks. After the mask data is specified in the write-mask register by using the load mask register (LMR) cycle, the old mask mode is invoked during the masked functions. The I/O mask data in the write-mask register maintains until another LMR operation is performed during the old mask mode. The LMR cycle is initiated by holding CAS, DT/OE, WB/WE and DSF1 “high” at the falling edge of RAS and by DSF1 “low” at the falling edge of CAS. The data presented on the Wi/IOi lines are subsequently latched into the write-mask register at the falling edge of either CAS or WB/WE, whichever occurs later. The old mask mode is reset to the new mask mode by a CAS before RAS refresh cycle (CBR). During the LMR cycle, the memory calls of the row address which is latched at the falling edge of RAS are refreshed. Figure 3. State Diagram of Mask Mode LMR Cycle CBR Cycle 48/62 TOSHIBA CORPORATION TC528267 7. LOAD COLOR REGISTER : LCR The TC528267 is provided with an on-chip 8-bits register (color register) for use during the block write or flash write function. Each bit of the color register corresponds to one of the DRAM I/O blocks. The load color register cycle is initiated by holding CAS, WB/WE, DT/OE and DSF1 “high” at the falling edge of RAS. The data presented on the Wi/IOi lines is subsequently latched into the color register at the falling edge of either CAS or WB/WE, whichever occurs later. During the load color register cycle, the memory cells on the row address latched at the falling edge of RAS are refreshed. 8. REFRESH The data in the DRAM requires periodic refreshing to prevent data loss. Refreshing is accomplished by performing a memory cycle at each of 512 rows in the DRAM array within the specified 8 ms refresh period. The TC528267 supports the conventional dynamic RAM refresh operations such as RAS only refresh, CAS before RAS refresh and hidden refresh. 8.1 CAS before RAS Refresh and Option Reset : CBR The CBR cycle reset the following functions, performing the CAS before RAS refresh operation at the same time. • To reset the old mask mode to the new mask mode for the masked functions. • To reset the stop register and remove the binary boundaries for the split SAM operation, The systems which implement neither the old mask mode nor the binary boundary in the SAM is recommended to use the CBR cycle for refresh operation. 49/62 TOSHIBA CORPORATION TC528267 8.2 CAS before RAS Refresh : CBRN The CBRN cycle performs only the CAS before RAS refresh operation. The systems which implement either the old mask mode or the binary boundary in the SAM usually use the CBRN cycle for refresh operation except for at the required stop register set or option reset cycles. The CBRN cycle must not be used during the initialization after power-up, 8.3 CAS before RAS Refresh and Stop Register Set : CBRS The CBRS cycle sets the stop register to place binary boundaries in each falf SAM, performing the CAS before RAS refresh operation at the same time. The CBRS cycle is initiated by CAS holding “low” and by WB /WE and DSF1 “high” at the falling edge of RAS. At the same time the data on the address pins, A0 - A8 is latched and the binary boundaries in each half SAM will be available when a split transfer operation is performed, Figure 4 . Stop Register and Binary Boundary Location 50/62 TOSHIBA CORPORATION TC528267 NOTE OE control of Extended Fast Page mode Read cycle When OE is toggled while CAS is “Low” level in fast page mode read cycle, the same data is valid on WI/ O. However, the data will not be valid when OE goes low with CAS high condition. The data will come out in following CAS cycle. Such a OE control have to satisfy tOEP (10ns min), tECS (10ns min), tECH (10ns min). Please refer following Figure. DATA TRANSFER OPERATION The TC528267 features two types of internal bidirectional data transfer capability between the RAM and the SAM, as shown in Figure 5. During a normal transfer, 512 words by 8 bits of data can be loaded from RAM to SAM (Read Transfer) or from SAM to RAM (Write Transfer), During a split transfer, 256 words by 8 bits of data can be loaded from the lower / upper half of the RAM into the lower / upper half of the SAM (Split Read Transfer) or from the lower/upper half of the SAM into the lower/upper half of the RAM (Split Write Transfer). The normal transfer and split transfer modes are controlled by the DSF1 input signal Figure 5. (a) Normal Transfer (b) Split Transfer 51/62 TOSHIBA CORPORATION TC528267 Table 3. shows the truth table of each Transfer Modes RAS Mnemonic Transfer Transfer Transfer Mode SAM Port Mode Code Direction Bit CAS DT/OE WB/WE DFS1 H L H L RT Read Transfer RAM → SAM 512x8 Input → Output H L L L WT Write Transfer (New/Old Mask) SAM → RAM 512x8 Output → Input H L H H SRT Split Read Transfer RAM → SAM 256x8 Not changed H L L H SWT Split Write Transfer (New/Old Mask) SAM → RAM 256x8 Not changed 9. READ TRANSFER CYCLE : RT A read transfer consists of loading a selected row of data from the RAM array into the SAM register. A read transfer is invoked by holding CAS “high”, DT/OE “low” WB/WE “high” and DSF1 “low” at the falling edge of RAS. The row address selected at the falling edge of RAS determines the RAM row to be transferred into the SAM. At the same time, the SAM port is set into the output mode. The start address of the serial pointer of the SAM (TAP address) is determined by the column address selected at the falling edge of CAS. By doing a tight timing control between the DT/OE rising edge and SC falling edge, a real time read transfer operation can also be performed. Figure 6 shows the operation block diagram for read transfer operation. Figure 6. Block Diagram for Read Transfer Operation In a read transfer cycle (which is preceded by a write transfer cycle), the SC clock must be held at a constant VIL or VIH, after the SC high time has been satisfied. A rising edge of the SC clock must not occur until after the specified delay tTSD from the rising edge of DT/OE and the falling edge of RAS and CAS , as shown in READ TRANSFER CYCLE timing chart. 52/62 TOSHIBA CORPORATION TC528267 10. WRITE TRANSFER CYCLE : WT A write transfer cycle consists of loading the content of the SAM register into a selected row of the RAM array. The write transfer is invoked by holding CAS “high”, DT/OE “low”, WB/WE “low”, and DSF1 “low” at the falling edge of RAS. The row address selected at the falling edge of RAS determines the RAM row address into which the data will be transferred. The column address selected at the falling edge of CAS determines the start address of the serial pointer of the SAM (TAP address). After the write transfer is completed, the SIO lines are set in the input mode so that serial data synchronized with the SC clock can be loaded. The write transfer is selectively controlled per RAM I/O block by setting the mask data on the Wi/IOi lines at the falling edge of RAS (some as in the write-per-bit operation). Before the serial clock starts loading the data into the SAM through SIO pins, the write transfer operation with all I/O blocks disabled must be performed in order to change the SAM port from output. Please note that the conventional pseudo write transfer is not available in the TC528267. The mask function is switched between the new and old mask mode by the LMR and CBR cycle. Figure 7. Block Diagram for Write Transfer Operation When consecutive write transfer operations are performed, new data must not be written into the serial register until the RAS cycle of the preceding write transfer is completed. Consequently, the SC clock must be held at a constant VIL or VIH during the RAS cycle. A rising edge of the SC clock is only allowed after the specified delay tSRD from the rising edge of RAS, at which time a new row of data can be written in the serial register. 53/62 TOSHIBA CORPORATION TC528267 11. SPLIT READ TRANSFER CYCLE : SRT A split read transfer consists of loading 256 words by 8 bits of data from a selected row of the half RAM array into the corresponding half SAM in stand-by mode. Serial data can be shifted out of the other half of the SAM in active mode simultaneously, as shown in Figure 8. The most significant column address (A8C) is controlled internally to determine which half of the SAM will be reloaded from the RAM array. During the split read transfer operation, the RAM port control signals do not have to be synchronized with the serial clock SC, thus eliminating the timing restrictions as in the case of real time read transfers. Prior to the execution of the split read transfer operation, a (normal) transfer operation must be performed to determine the absolute tap address location. QSF is an output that indicates which half of the SAM is in the active state. QSF changes state when the last SC clock is applied to the active SAM, as shown in Figure 9. Active SAM QSF Level lower SAM “Low” upper SAM “High” Figure 8. Split Read Transfer Figure 9. Example of Consecutive Read Transfer Operations 54/62 TOSHIBA CORPORATION TC528267 12. SPLIT WRITE TRANSFER : MSWT A split write transfer is the similar function to the split read transfer. The difference is that the transfer direction is from the stand-by half SAM into a selected row of the corresponding half RAM array. Also, serial data can be shifted into the other half of the SAM simultaneously, as shown in Figure 10. New and old mask capability is supported in the MSWT cycle as is in the write transfer operation. Prior to the execution of the split write transfer operation, a write transfer operation, in which all I/O blocks are usually disabled, must precede to switch the SAM port from output mode to input mode and to set the initial TAP location for the serial input operation. Figure 10. Block Diagram for Split Write Transfer Figure 11. Example of Consecutive Write Transfer Operations 55/62 TOSHIBA CORPORATION TC528267 NOTES (1) Transfer operation without CAS. The SAM tap location is undefined if CAS is maintained at a constant “high” level during a transfer cycle. A transfer cycle with CAS held “high” is, hence, not allowed. (2) In the case of multiple split transfers performed into the same half SAM, the tap location specified during the last split transfer, before QSF toggles, will prevail, as shown below. (3) Split transfer operation allowable period. Figure 12 illustrates the relationship between the serial clock SC and the special function output QSF during split read / write transfers and highlights the time periods where split transfers are allowed, relative to SC and QSF. A split transfer is not allowed during to tSTH + tSTS. In the case that the CBRS operation is executed and the binary boundary in each half SAM is set or updated, an additional period is applied, as shown in Figure 12. Figure 12. Split Transfer Operation Allowable Periods The stop register and binary boundary are explained in the CBRS operation and the SAM port operation. 56/62 TOSHIBA CORPORATION TC528267 (4) A normal transfer (read/write) may be performed following split transfer operation provided that a tSTS minimun delay is satisfied after the QSF signal toggles. (5) Binary-Boundary SET/RESET Cycle Timing. When the address counter of serial-access-memory (SAM) pointed as the last address of each boundary address. (15, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175, 191, 207, 223, 239, 255, 271, 287, 303, 319, 335, 351, 367, 383, 399, 415, 431, 447, 463, 479, 495, 511), the boundary-set or change by CBRS-cycle or the boundary-reset by CBR-cycle may cause the unexpected operation of SAM counter or QSF status. If the system design with these timing is required. Please contact to our local sales office. SAM PORT OPERATION The TC528267 is provided with 512 words by 8 bits serial access memory (SAM) which can be operated in the single register mode or the split register mode. High speed serial read or write operations can be performed through the SAM port independent of the RAM port operation. 13. SINGLE REGISTER SERIAL READ OPERATION Serial data can be read out of the SAM port after a read transfer has been performed. The read transfer operation changes the SAM port to the output mode. At every rising edge of the serial clock, the data is read out sequentially starting from the selected tap location to the most significant bit and then wraps around to the least significant bit, as illustrated below. Subsequent real-time read transfer may be performed on-the-fly as many times as desired. 14. SINGLE REGISTER SERIAL WRITE OPERATION During the serial write operation, the data is written into the SAM at every rising edge of the serial clock. A write transfer cycle, at which all I/Os are usually masked, must be performed to change the SAM port to the input mode. The tap location, which is the start address of the serial write, is set by the column address at the falling edge of CAS. After the data is filled in the SAM, the serial clock must stop toggling and a write transfer cycle is subsequently used to load the SAM data into the RAM selected by the row address at the falling edge of RAS. The tap address is set during the same cycle for the next serial write opration. 57/62 TOSHIBA CORPORATION TC528267 15. SPLIT REGISTER MODE The split register mode realizes continuous serial read or write operation. The data can be shifted into or out of one half of the SAM while a split read or write transfer is being performed on the other half of the SAM. Thus, the tight timing control at a real time read operation is eliminated with the split read operation. A normal read / write transfer operation must precede any split read/write transfer operation in order to set the SAM port into output mode or input mode, as the split read or write transfer operations will not change the SAM port mode. Also, a CAS before RAS refresh and stop register set cycle (CBRS) can be performed to specify the binary boundaries in the SAM. In the split register mode, serial data can be read from or written into one of the split registers starting from any of the 256 tap locations. The data is read or written sequentially from the tap location to the most significant bit (255 or 511) of the first split SAM and then the SAM pointer moves to the tap location selected for the second split SAM to read or write the data sequentially to the most significant bit (255 or 511) and finally wraps around to the least significant bit, as illustrated in the example below. 16. SPLIT REGISTER MODE WITH BINARY BOUNDARY After a CBRS cycle is performed, the binary boundary, which is stated in 8.3. CAS before RAS refresh and stop register set, is set when a SRT cycle is performed. The serial data is read from or written into one half of the SAM starting the tap location to the next binary boundary, while another SRT cycle is performed. Then, the SAM pointer moves to the tap location in the other half SAM and the data is read from or written into the half SAM sequentially. If any SRT operation is not performed before the next boundary, the SAM pointer does not jump to the other half SAM, as illustrated in Figure 12. 58/62 TOSHIBA CORPORATION TC528267 .Figure 12. Operation of Split Register Mode with Binary Boundary The binary boundary is reset by a CBR cycle and the SAM operation mode returns to the normal split register mode, as shown in Figure 13. Fig. 14 shows the relation between CBR and SC on binary-boundary-reset. When Nth SC clock accesses old binary address is reset and (N + 1)th SC clock accesses old boundary address (old stop address) + 1 on the same split SAM, not jump to TAP address. Figure 13. Binary Boundary Reset 59/62 TOSHIBA CORPORATION TC528267 Figure 14. CBR and SC relation of binary-boundary-reset In an actual system which uses the binary boundary a CBRS cycle is executed to determine a type of the boundary location. Then, a normal RT transfers a row of data into the SAM and set the initial tap location at the same time. An SRT cycle follows it before the SAM pointer reaches to the boundary location. The SRT cycle makes the binary boundary jump effective, as illustrated in Figure 15. Figure 15. Binary Boundary Jump Set Sequence There are additional timing specifications, tTSAA and tSAAT to determine the period that does not allow a split transfer, as illustrated in Figure 16. 60/62 TOSHIBA CORPORATION TC528267 Figure 16. Timing Specification to allow SRT operation POWER-UP Power must be applied to the RAS and DT/OE input signals to pull them “high” before or at the same time as the VCC supply is turned on. After power-up, a pause of 200 µseconds minimum is required with RAS and DT/OE held “high”. After the pause, a minimum of 8 CBR dummy cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer operations can begin. During the initialization period, the DT/OE signal must be held “high”. INITIAL STATE AFTER POWER-UP When power is achieved with RAS, CAS, DT/OE and WB/WE held “high”, the internal state of the TC528267 is automatically set as follows. However, the initial state can not be guaranteed for various power-up conditions and input signal levels. Therefore, it is recommended that the initial state be set after the initialization of the device is performed (200 µseconds pause followed by a minimum of 8 CBR cycles) and before valid operations begin. State after power-up SAM port Input Mode QSF High-Impedance Color Register all “0” Write Mask Register Write Enable TAP pointer Invalid Stop Register Default Case 61/62 TOSHIBA CORPORATION TC528267 62/62 TOSHIBA CORPORATION