This file is raw output from pdftotext and may not be ideal for distribution. If you are a maintainer for Hackipedia, please sit down when you have time and clean this text version up. Source PDF: /mnt/fw-js/docs/Disassembly and analysis/documentation - Components of Pinnacle MovieBox USB/HY57V643220C (onboard DRAM)/HY57V643220C (2).pdf Like all conversions the text below should be fully readable as UTF-8 unicode text. --------------------------------------------------------------- HY57V643220CT(P) 4 Banks x 512K x 32Bit Synchronous DRAM DESCRIPTION The Hynix HY57V643220CT(P) is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applica- tions which require wide data I/O and high bandwidth. HY57V643220CT(P) is organized as 4banks of 524,288x32. HY57V643220CT(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • JEDEC standard 3.3V power supply • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms • JEDEC standard 400mil 86pin TSOP-II with 0.5mm of • Programmable Burst Length and Burst Type pin pitch - 1, 2, 4, 8 or full page for Sequential Burst • All inputs and outputs referenced to positive edge of system clock - 1, 2, 4 or 8 for Interleave Burst • Data mask function by DQM0,1,2 and 3 • Programmable CAS Latency ; 2, 3 Clocks • Internal four banks operation • Burst Read Single Write operation ORDERING INFORMATION Part No. Clock Frequency Power Organization Interface Package HY57V643220C(L)T(P)-47 212MHz HY57V643220C(L)T(P)-5 200MHz HY57V643220C(L)T(P)-55 183MHz HY57V643220C(L)T(P)-6 166MHz Normal/ 4Banks x 400mil 86pin LVTTL Low Power 512Kbits x32 TSOP II HY57V643220C(L)T(P)-7 143MHz HY57V643220C(L)T(P)-8 125MHz HY57V643220C(L)T(P)-P 100MHz HY57V643220C(L)T(P)-S 100MHz NOTE) Hynix supports lead free part for each speed grade with same specification. This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9 / Feb. 2004 1 HY57V643220CT(P) PIN CONFIGURATION VDD 1 86 VSS DQ0 2 85 DQ 15 VDDQ 3 84 VSSQ DQ1 4 83 DQ 14 DQ2 5 82 DQ 13 VSSQ 6 81 VDDQ DQ3 7 80 DQ 12 DQ4 8 79 DQ 11 VDDQ 9 78 VSSQ DQ5 10 77 DQ 10 DQ6 11 76 DQ9 VSSQ 12 75 VDDQ DQ7 13 74 DQ8 NC 14 73 NC VDD 15 72 VSS DQM0 16 71 DQM 1 /W E 17 70 NC /C A S 18 69 NC /R A S 19 68 CLK /C S 20 67 CKE 8 6 p in T S O P II NC 21 66 A9 BA0 4 0 0 m il x 8 7 5 m il 65 22 A8 BA1 23 0 .5 m m p in p itc h 64 A7 A 1 0 /A P 24 63 A6 A0 25 62 A5 A1 26 61 A4 A2 27 60 A3 DQM2 28 59 DQM 3 VDD 29 58 VSS NC 30 57 NC D Q 16 31 56 DQ 31 VSSQ 32 55 VDDQ D Q 17 33 54 DQ 30 D Q 18 34 53 DQ 29 VDDQ 35 52 VSSQ D Q 19 36 51 DQ 28 D Q 20 37 50 DQ 27 VSSQ 38 49 VDDQ D Q 21 39 48 DQ 26 D Q 22 40 47 DQ 25 VDDQ 41 46 VSSQ D Q 23 42 45 DQ 24 VDD 43 44 VSS PIN DESCRIPTION PIN PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge CLK Clock of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states CKE Clock Enable among power down, suspend or self refresh CS Chip Select Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity BA0, BA1 Bank Address Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7 A0 ~ A10 Address Auto-precharge flag : A10 Row Address Strobe, RAS, CAS and WE define the operation RAS, CAS, WE Column Address Strobe, Write Refer function truth table for details Enable DQM0~3 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers NC No Connection No connection Rev. 0.9 / Feb. 2004 2 HY57V643220CT(P) FUNCTIONAL BLOCK DIAGRAM 512Kbit x 4banks x 32 I/O Synchronous DRAM Self Refresh Logic Refresh & Timer Counter CLK 512Kx32 Bank 3 Row Active Row 512Kx32 Bank 2 CKE Pre X decoder Decoder 512Kx32 Bank 1 X decoder CS 512Kx32 Bank 0 State Machine X decoder RAS DQ0 Sense AMP & I/O Gate X decoder Memory DQ1 I/O Buffer & Logic CAS Cell Array WE Column Column DQM0 Active Pre DQM1 Decoder DQ30 DQM2 DQ31 DQM3 Y decoder Column Add Bank Select Counter A0 Address A1 Register Address buffers Burst Counter A10 BA0 CAS Latency BA1 Mode Register Data Out Control Pipe Line Control Rev. 0.9 / Feb. 2004 3 HY57V643220CT(P) ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TSTG -55 ~ 125 °C Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W Soldering Temperature . Time TSOLDER 260 . 10 °C ⋅ Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION (TA=0 to 70°C) Parameter Symbol Min Typ. Max Unit Note Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1,2 Input high voltage VIH 2.0 3.0 VDDQ + 0.3 V 1,3 Input low voltage VIL VSSQ - 0.3 0 0.8 V 1,4 Note : 1.All voltages are referenced to VSS = 0V 2.VDD/VDDQ(min) is 3.15V for HY57V643220C(L)T-47/5/55/6 3.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes 4.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes AC OPERATING CONDITION (TA=0 to 70°C, 3.0V ≤VDD ≤3.6V, VSS=0V - Note1) Parameter Symbol Value Unit Note AC input high / low level voltage VIH / VIL 2.4/0.4 V Input timing measurement reference level voltage Vtrip 1.4 V Input rise / fall time tR / tF 1 ns Output timing measurement reference level Voutref 1.4 V Output load capacitance for access time measurement CL 30 pF 2 Note : 1.3.15V ≤VDD ≤3.6V is applied for HY57V643220C(L)T-47/5/55/6 2.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF) For details, refer to AC/DC output load circuit Rev. 0.9 / Feb. 2004 4 HY57V643220CT(P) CAPACITANCE (TA=25×C, f=1MHz, VDD=3.3V) Parameter Pin Symbol Min Max Unit Input capacitance CLK CI1 2.5 3.5 pF A0 ~ A10, BA0, BA1, CKE, CS, RAS, CAS, WE, CI2 2.5 3.8 pF DQM0~3 Data input / output capacitance DQ0 ~ DQ31 CI/O 4 6.5 pF OUTPUT LOAD CIRCUIT Vtt=1.4V Vtt=1.4V RT=500 Ω RT=50 Ω Output Output Z0 = 50Ω 30pF 30pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (DC operating conditions unless otherwise noted) Parameter Symbol Min. Max Unit Note Input leakage current ILI -1 1 uA 1 Output leakage current ILO -1 1 uA 2 Output high voltage VOH 2.4 - V IOH = -2mA Output low voltage VOL - 0.4 V IOL = +2mA Note : 1.VIN = 0 to 3.6V, All other pins are not under test = 0V 2.DOUT is disabled, VOUT=0 to 3.6V Rev. 0.9 / Feb. 2004 5 HY57V643220CT(P) DC CHARACTERISTICS II (DC operating conditions unless otherwise noted) Speed Parameter Symbol Test Condition Unit Note -47 -5 -55 -6 -7 -8 -P -S Burst Length=1, One bank active Operating Current IDD1 tRAS ≥tRAS(min), tRP ≥tRP(min), 220 200 190 180 170 150 150 150 mA 1 IOL=0mA Precharge Standby IDD2P CKE ≤VIL(max), tCK = 15ns 2 Current mA in power down mode IDD2PS CKE ≤VIL(max), tCK = ∞ 2 CKE ≥VIH(min), CS ≥VIH(min), tCK = 15ns IDD2N Input signals are changed one time 15 Precharge Standby during 2clks. All other pins ≥VDD-0.2V or Current ≤0.2V mA in non power down mode CKE ≥ VIH(min), tCK = ∞ IDD2NS 10 Input signals are stable. IDD3P CKE ≤VIL(max), tCK = 15ns 3 Active Standby Current mA in power down mode IDD3PS CKE ≤VIL(max), tCK = ∞ 3 CKE ≥VIH(min), CS ≥VIH(min), tCK = 15ns IDD3N Input signals are changed one time 40 Active Standby Current during 2clks. All other pins ≥VDD-0.2V or in non power down mode ≤0.2V mA IDD3NS CKE ≥ VIH(min), tCK = ∞Input signals are 25 stable tCK ≥ tCK(min), CL=3 290 280 260 240 210 180 180 180 Burst Mode Operating Current IDD4 tRAS ≥ tRAS(min), IOL=0mA mA 1 All banks active CL=2 160 160 160 160 160 160 160 Auto Refresh Current IDD5 tRRC ≥ tRRC(min), 2 banks active 260 250 235 220 210 190 210 190 mA 2 2 3 Self Refresh Current IDD6 CKE ≤ 0.2V mA 1 4 Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V643220CT(P)-47/5/55/6/7/8/P/S 4.HY57V643220CLT(P)-47/5/55/6/7/8/P/S Rev. 0.9 / Feb. 2004 6 HY57V643220CT(P) AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -47 -5 -55 -6 -7 -8 -P -S Parameter Symbol Unit Note Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max CAS Latency = 3 tCK3 4.7 5 5.5 6 7 8 10 10 ns System clock 1000 1000 1000 1000 1000 1000 1000 1000 cycle time CAS Latency = 2 tCK2 10 10 10 10 10 -10 10 12 ns Clock high pulse width tCHW 1.65 - 2 - 2.25 - 2.5 - 3 - 3 - 3 - 3 - ns 1 Clock low pulse width tCLW 1.65 - 2 - 2.25 - 2.5 - 3 - 3 - 3 - 3 - ns 1 CAS Latency = 3 tAC3 - 4.5 - 4.5 - 5 - 5.5 - 5.5 - 6 - 6 - 6 ns Access time from 2 clock CAS Latency = 2 tAC2 - 6 - 6 - 6 - 6 - 6 - 6 - 6 - 6 ns Data-out hold time tOH 1.5 - 1.5 - 2 - 2 - 2 - 2 - 2 - 2 - ns 3 Data-Input setup time tDS 1.3 - 1.5 - 1.5 - 1.5 - 1.75 - 2 - 2 - 2 - ns 1 Data-Input hold time tDH 0.8 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns 1 Address setup time tAS 1.3 - 1.5 - 1.5 - 1.5 - 1.75 - 2 - 2 - 2 - ns 1 Address hold time tAH 0.8 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns 1 CKE setup time tCKS 1.3 - 1.5 - 1.5 - 1.5 - 1.75 - 2 - 2 - 2 - ns 1 CKE hold time tCKH 0.8 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns 1 Command setup time tCS 1.3 - 1.5 - 1.5 - 1.5 - 1.75 - 2 - 2 - 2 - ns 1 Command hold time tCH 0.8 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns 1 CLK to data output in low Z-time tOLZ 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns CAS Latency = 3 tOHZ3 - 4 - 4.5 - 5 - 5.5 - 5.5 - 6 - 6 - 6 ns CLK to data output in high Z-time CAS Latency = 2 tOHZ2 - 6 - 6 - 6 - 6 - 6 - 6 - 6 - 6 ns Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v 3.Data-out hold time to be measured under 30pF load condition, without Vt termination Rev. 0.9 / Feb. 2004 7 HY57V643220CT(P) AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) -47 -5 -55 -6 -7 -8 -P -S Parameter Symbol Unit Note Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Operation tRC 51.7 - 55 - 55 - 60 - 63 - 64 - 70 - 70 - ns RAS cycle time Auto Refresh tRRC 51.7 - 55 - 55 - 60 - 63 - 64 - 70 - 70 - ns RAS to CAS delay tRCD 14.1 - 15 - 16.5 - 18 - 20 - 20 - 20 - 20 - ns 100 100 100 100 100 100 100 RAS active time tRAS 37.6 100K 38.7 38.7 42 42 48 50 50 ns K K K K K K K RAS precharge time tRP 14.1 - 15 - 16.5 - 18 - 20 - 20 - 20 - 20 - ns RAS to RAS bank active delay tRRD 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK CAS to CAS delay tCCD 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Write command to data-in delay tWTL 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK Data-in to precharge command tDPL 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Data-in to active command tDAL 4 - 4 - 4 - 4 - 4 - 4 - 4 - 4 - CLK DQM to data-out Hi-Z tDQZ 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK DQM to data-in mask tDQM 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK MRS to new command tMRD 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK CAS Latency = 3 tPROZ3 3 - 3 - 3 - 3 - 3 - 3 - 3 - 3 - CLK Precharge to data output Hi-Z CAS Latency = 2 tPROZ2 - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK Power down exit time tPDE 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Self refresh exit time tSRE 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK 1 Refresh Time tREF - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms Note : 1. A new command can be given tRRC after self refresh exit Rev. 0.9 / Feb. 2004 8 HY57V643220CT(P) DEVICE OPERATING OPTION TABLE HY57V643220C(L)T(P)-47 CAS Latency tRCD tRAS tRC tRP tAC tOH 212MHz(4.7ns) 3CLKs 3CLKs 37.6ns 12CLKs 3CLKs 4ns 1.5ns 200MHz(5ns) 3CLKs 3CLKs 38.5ns 11CLKs 3CLKs 4.5ns 1.5ns 183MHz(5.5ns) 3CLKs 3CLKs 38.5ns 10CLKs 3CLKs 5ns 2ns HY57V643220C(L)T(P)-5 CAS Latency tRCD tRAS tRC tRP tAC tOH 200MHz(5ns) 3CLKs 3CLKs 38.5ns 11CLKs 3CLKs 4.5ns 1.5ns 183MHz(5.5ns) 3CLKs 3CLKs 38.5ns 10CLKs 3CLKs 5ns 2ns 166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns HY57V643220C(L)T(P)-55 CAS Latency tRCD tRAS tRC tRP tAC tOH 183MHz(5.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5ns 2ns 166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns HY57V643220C(L)T(P)-6 CAS Latency tRCD tRAS tRC tRP tAC tOH 166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.5ns HY57V643220C(L)T(P)-7 CAS Latency tRCD tRAS tRC tRP tAC tOH 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns HY57V64322C(L)T(P)-8 CAS Latency tRCD tRAS tRC tRP tAC tOH 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns 83MHz(12ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.5ns Rev. 0.9 / Feb. 2004 9 HY57V643220CT(P) HY57V643220C(L)T(P)- P CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.5ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.5ns HY57V643220C(L)T(P)-S CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.5ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.5ns Rev. 0.9 / Feb. 2004 10 HY57V643220CT(P) COMMAND TRUTH TABLE A10/ Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR BA Note AP Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X RA V Read L H X L H L H X CA V Read with Autoprecharge H Write L H X L H L L X CA V Write with Autoprecharge H Precharge All Banks H X H X L L H L X X Precharge selected Bank L V Burst Stop H X L H H L X X DQM H X V X Auto Refresh H H L L L H X X A9 Pin High Burst-READ-Single-WRITE H X L L L L X (Other Pins OP code) Entry H L L L L H X Self Refresh1 H X X X X Exit L H X L H H H H X X X Entry H L X Precharge power L H H H X down H X X X Exit L H X L H H H H X X X Entry H L X Clock L V V V X Suspend Exit L H X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don’t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation Rev. 0.9 / Feb. 2004 11 HY57V643220CT(P) PACKAGE INFORMATION 400mil 86pin Thin Small Outline Package Unit : mm(inch) 11.938(0.4700) 22.327(0.8790) 11.735(0.4620) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 1.194(0.0470) 0.050(0.0020) 0.991(0.0390) 0.21(0.008) 5deg 0.597(0.0235) 0.210(0.0083) 0.50(0.0197) 0deg 0.406(0.0160) 0.120(0.0047) 0.18(0.007) Rev. 0.9 / Feb. 2004 12