This file is raw output from pdftotext and may not be ideal for distribution. If you are a maintainer for Hackipedia, please sit down when you have time and clean this text version up. Source PDF: /mnt/fw-js/docs/Hardware/Other, misc/7216L 16 x 16 PARALLEL CMOS MULTIPLIERS.pdf Like all conversions the text below should be fully readable as UTF-8 unicode text. --------------------------------------------------------------- 16 x 16 PARALLEL IDT7216L CMOS MULTIPLIERS IDT7217L Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • 16 x 16 parallel multiplier with double precision product The IDT7216/IDT7217 are high-speed, low-power • 16ns clocked multiply time 16 x 16-bit multipliers ideal for fast, real time digital signal • Low power consumption: 120mA processing applications. Utilization of a modified Booths • Produced with advanced submicron CMOS high perfor- algorithm and IDT’s high-performance, submicron CMOS mance technology technology, has achieved speeds comparable to bipolar (20ns • IDT7216L is pin- and function compatible with TRW max.), at 1/10 the power consumption. MPY016H/K and AMD Am29516 The IDT7216/IDT7217 are ideal for applications requiring high-speed multiplication such as fast Fourier transform • IDT7217L requires a single clock with register enables analysis, digital filtering, graphic display systems, speech making it pin- and function compatible with AMD synthesis and recognition and in any system requirement Am29517 where multiplication speeds of a mini/microcomputer are • Configured for easy array expansion inadequate. • User-controlled option for transparent output register All input registers, as well as LSP and MSP output regis- mode ters, use the same positive edge-triggered D-type flip-flop. In • Round control for rounding the MSP the IDT7216, there are independent clocks (CLKX, CLKY, • Input and output directly TTL-compatible CLKM, CLKL) associated with each of these registers. The • Three-state output IDT7217 has only a single clock input (CLK) and three register • Available in Top Braze, DIP, PLCC, Flatpack and Pin enables. ENX and ENY control the two input registers, while Grid Array ENP controls the entire product. • Military product compliant to MIL-STD-883, Class B The IDT7216/IDT7217 offer additional flexibility with the FA • Standard Military Drawing #5962-86873 is listed on this control and MSPSEL functions. The FA control formats the function for IDT7216 and Standard Military Drawing output for two’s complement by shifting the MSP up one bit #5962-87686 is listed for this function for IDT7217. and then repeating the sign bit in the MSB of the LSP. The • Speeds available: Commercial: L16/20/25/35/45/55/65 Military: L20/25/30/40/55/65/75 FUNCTIONAL BLOCK DIAGRAMS IDT7216 IDT7217 XM X15-0 RND YM Y15-0/P15-0 XM X15-0 RND YM Y15-0/P15-0 16 16 16 16 XREGISTER REGISTER YREGISTER XREGISTER REGISTER YREGISTER CLKY CLK CLKX ENX OEL OEL ENY MULTIPLIER MULTIPLIER ARRAY ARRAY FA FORMAT ADJUST FA FORMAT ADJUST MSP LSP MSP LSP FT REGISTER REGISTER FT REGISTER REGISTER CLKM 16 16 16 16 CLKL ENP MSPSEL MULTIPLEXER MSPSEL MULTIPLEXER OEP OEP 16 16 PRODUCT PRODUCT MSPOUT (P31 - P16) 2580 drw 01 MSPOUT (P31 - P16) 2580 drw 02 The IDT Logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995 ©1995 Integrated Device Technology, Inc. 11.3 DSC-2023/6 1 IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS MILITARY AND COMMERCIAL TEMPERATURE RANGES DESCRIPTION (Cont’d.) MSPSEL low selects the MSP to be available at the product The IDT7216/IDT7217 multipliers are manufactured in output port, while a high selects the LSP to be available. compliance with the latest revision of MIL-STD-883, Class B, Keeping this pin low will ensure compatibility with the TRW making them ideally suited to applications demanding the MPY016H. highest level of performance and reliability. PIN CONFIGURATIONS IDT7216 IDT7217 X4 1 64 X5 X4 1 64 X5 X3 2 63 X6 X3 2 63 X6 X2 3 62 X7 X2 3 62 X7 X1 4 61 X8 X1 4 61 X8 X0 5 60 X9 X0 5 60 X9 OEL 6 59 X10 OEL 6 59 X10 CLKL 7 58 X11 CLK 7 58 X11 CLKY 8 57 X12 ENY 8 57 X12 P0, Y0 9 56 X13 P0, Y0 9 56 X13 P1, Y1 10 55 X14 P1, Y1 10 55 X14 P2, Y2 11 54 X15 P2, Y2 11 54 X15 P3, Y3 12 53 CLKX P3, Y3 12 53 ENX P4, Y4 13 52 RND P4, Y4 13 52 RND P5, Y5 14 51 XM P5, Y5 14 51 XM P6, Y6 15 50 YM P6, Y6 15 50 YM P7, Y7 16 C64-2 49 VCC P7, Y7 16 C64-2 49 VCC P8, Y8 17 48 VCC P8, Y8 17 48 VCC P9, Y9 18 47 GND P9, Y9 18 47 GND P10, Y10 19 46 GND P10, Y10 19 46 GND P11, Y11 20 45 MSPSEL P11, Y11 20 45 MSPSEL P12, Y12 21 44 FT P12, Y12 21 44 FT P13, Y13 22 43 FA P13, Y13 22 43 FA P14, Y14 23 42 OEP P14, Y14 23 42 OEP P15, Y15 24 41 CLKM P15, Y15 24 41 ENP P0, P16 25 40 P15 , P31 P0, P16 25 40 P15 , P31 P1, P17 26 39 P14 , P30 P1, P17 26 39 P14 , P30 P2, P18 27 38 P13 , P29 P2, P18 27 38 P13 , P29 P3, P19 28 37 P12 , P28 P3, P19 28 37 P12 , P28 P4, P20 29 36 P11 , P27 P4, P20 29 36 P11 , P27 P5, P21 30 35 P10 , P26 P5, P21 30 35 P10 , P26 P6, P22 31 34 P9, P25 P6, P22 31 34 P9, P25 P7, P23 32 33 P8, P24 P7, P23 32 33 P8, P24 2580 drw 03 2580 drw 04 64-PIN DIP 64-PIN DIP TOP VIEW TOP VIEW 11.3 2 IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS (Cont’d.) IDT7216/IDT7217 11 NC X13 X15 RND YM VCC GND FT OEP CLKX CLKM 10 X11 X12 X14 or XM VCC GND MSP- FA or NC ENX* SEL ENP* P30, P31, 09 X9 X10 P14 P15 08 X7 X8 P28, P29, P12 P13 07 X5 X6 P26, P27, P10 P11 P24, P25, 06 X3 X4 G68-2 P8 P9 P22, P23, 05 X1 X2 P6 P7 P20, P21, 04 OEL X0 P4 P5 CLKY CLKL P18, P19, 03 or or ENY* CLK* P2 P3 Y0, Y2, Y4, Y6, Y8, Y10, Y12, Y14, P16, P17, 02 NC P0 P2 P4 P6 P8 P10 P12 P14 P0 P1 01 Y1, Y3, Y5, Y7, Y9, Y11, Y13, Y15, NC P1 P3 P5 P7 P9 P11 P13 P15 Pin 1 A B C D E F G H J K L Designator *Pin designation for IDT7217 2580 drw 05 PGA TOP VIEW 11.3 3 IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS (Cont’d.) IDT7216 IDT7217 MSPSEL MSPSEL CLKX GND GND GND GND RND RND OEP OEP ENX ENP VCC VCC VCC VCC X15 X14 X13 X13 X15 X14 FA FA YM XM YM XM FT FT 64636261 605958575655 545352 515049 64636261 605958575655 545352 515049 P15, P31 1 48 X12 P15, P31 1 48 X12 P14, P30 2 47 X11 P14, P30 2 47 X11 P13, P29 3 46 X10 P13, P29 3 46 X10 P12, P28 4 45 X9 P12, P28 4 45 X9 P11, P27 5 44 X8 P11, P27 5 44 X8 P10, P26 6 43 X7 P10, P26 6 43 X7 P9, P25 7 42 X6 P9, P25 7 42 X6 P8, P24 8 41 X5 P8, P24 8 41 X5 P7, P23 9 F64-1 40 X4 P7, P23 9 F64-1 40 X4 P6, P22 10 39 X3 P6, P22 10 39 X3 P5, P21 11 38 X2 P5, P21 11 38 X2 P4, P20 12 37 X1 P4, P20 12 37 X1 P3, P19 13 36 X0 P3, P19 13 36 X0 P2, P18 14 35 OEL P2, P18 14 35 OEL P1, P17 15 34 CLKL P1, P17 15 34 CLK P0, P16 16 33 CLKY P0, P16 16 33 ENY 17181920 212223242526 272829 303132 17181920 212223242526 272829 303132 P15, Y15 P14, Y14 P13, Y13 P12, Y12 P11, Y11 P10, Y10 P6, Y6 P4, Y4 P3, Y3 P1, Y1 P0, Y0 P15, Y15 P13, Y13 P6, Y6 P4, Y4 P1, Y1 P0, Y0 P9, Y9 P8, Y8 P7, Y7 P5, Y5 P14, Y14 P12, Y12 P11, Y11 P10, Y10 P7, Y7 P5, Y5 P3, Y3 P2, Y2 P2, Y2 P9, Y9 P8, Y8 2580 drw 06 2580 drw 07 64-LEAD FLATPACK 64-LEAD FLATPACK TOP VIEW TOP VIEW IDT7216 IDT7217 CLKY CLKL OEL ENY OEL CLK X11 X12 X10 NC X11 X7 X12 X10 X9 X8 X6 X5 X4 X3 X2 X1 X0 NC X3 X9 X8 X7 X5 X4 X2 X0 X6 X1 60 59 58 5756 5554 53 5251 50 4948 47 46 45 44 60 59 58 5756 5554 53 5251 50 4948 47 46 45 44 X13 61 43 NC X13 61 X14 62 43 NC 42 P0, Y0 X14 62 42 P0, Y0 X15 63 41 P1, Y1 X15 63 41 P1, Y1 CLKX 64 40 P2, Y2 40 P2, Y2 RND 65 39 P3, Y3 ENX 64 RND 65 39 P3, Y3 XM 66 38 P4, Y4 XM 66 38 P4, Y4 YM 67 37 P5, Y5 YM 67 37 P5, Y5 VCC 68 36 P6, Y6 VCC68 VCC 1 J68-1 36 P6, Y6 L68-1, L68-1 35 P7, Y7 VCC 1 J68-1 L68-1, L68-1 35 P7, Y7 GND 2 34 P8, Y8 GND 3 33 P9, Y9 GND 2 34 P8, Y8 32 P10, Y10 GND 3 33 P9, Y9 MSPSEL 4 32 P10, Y10 FT 5 31 P11, Y11 MSPSEL 4 FA 6 30 P12, Y12 FT 5 31 P11, Y11 OEP 7 29 P13, Y13 FA 6 30 P12, Y12 CLKM 8 28 P14, Y14 OEP 7 29 P13, Y13 NC 9 27 P15, Y15 ENP 8 28 P14, Y14 NC 9 27 P15, Y15 10 1112 13 14 1516 17 1819 20 212223 24 25 26 10 1112 13 14 1516 17 1819 20 2122 23 24 25 26 P3, P19 NC P15, P31 P13, P29 P12, P28 P11, P27 P10, P26 P8, P24 P6, P22 P4, P20 P2, P18 P1, P17 P0, P16 P14, P30 P9, P25 P7, P23 P5, P21 P14, P30 NC P12, P28 P10, P26 P9, P25 P8, P24 P7, P23 P6, P22 P5, P21 P4, P20 P3, P19 P2, P18 P15, P31 P13, P29 P11, P27 P1, P17 P0, P16 2580 drw 08 2580 drw 09 PLCC PLCC TOP VIEW TOP VIEW 11.3 4 IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTIONS Pin Name I/O Description X0 - X15 I Data Inputs Y0 - Y15/ I/O Y0 - Y15 are data inputs P0 - P15 P0 - P15 are LSP register output, enabled when OEL = 0 P16 - P31 O Data Output (LSP or MSP) OEL I Output enable control for LSP (least significant product). When low enables P0 - P15. When high P0 - P15 tristated. OEP I Output enable control for MSP (most significant product). When low enables P16 - P31. When high P16 - P31 tristated. XM, YM I Mode control for each data word. Low designates unsigned data input and high designates two's complement. RND I "Round" control for rounding of MSP. When high, 1 is added to the most significant bit of LSP. This signal is affected by the state of FA pin. When FA = 1 and RND = 1, 1 is added to the 2-15 bit (P15). When RND = 1 and FA = 0, 1 is added to the 2 -16 bit (P14). The RND input is registered. It is clocked on the rising edge of the logical OR of CLKX and CLKY in the 7216 and on the rising edge of CLK in the 7217. Rounding always occurs in the positive direction which may introduce a systematic bias. MSPSEL I When low, MSP is output on P16 - P31 lines. When high, LSP is output on P16 - P31. FA I Format adjust control. When high, a full 32 bit product is selected. When low, a left shifted 31 bit product is selected with the sign bit replicated in the LSP. FA is normally high, except for certain fractional two's complement applications (see multiplier input / output formats). FT I Flow through control. When high, both MSP and LSP registers are by-passed. CLK I 7217 X, Y, RND, LSP and MSP register clock input. CLKX I 7216 X register clock input. Also clocks RND register. CLKY I 7216 Y register clock input. Also clocks RND register. CLKL I 7216 LSP register clock input. CLKM I 7216 MSP register clock input. ENX I 7217 X register clock enable. Also enables RND register clock. ENY I 7217 Y register clock enable. Also enables RND register clock. ABSOLUTE MAXIMUM RATINGS(1) CAPACITANCE (TA = +25°C, f = 1.0 MHz) Symbol Rating Commercial Military Unit Symbol Parameter(1) Conditions Max. Unit VCC Power Supply –0.5 to +7.0 –0.5 to +7.0 V CIN Input Capacitance VIN = 0V 10 pF Voltage COUT Output Capacitance VOUT = 0V 12 pF VTERM Terminal Voltage VCC + 0.5 VCC + 0.5 V NOTE: 2580 tbl 04 with Respect to 1. This parameter is measured at characterization and not tested. GND TA Operating 0 to +70 –55 to +125 °C Temperature TBIAS Temperature –55 to +125 –65 to +135 °C Under Bias TSTG Storage –55 to +125 –65 to +150 °C Temperature IOUT DC Output 50 50 mA Current NOTE: 2580 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 11.3 5 EL IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C) Commercial Military Symbol Parameter Test Conditions(1) Min. Typ.(1) Max. Min. Typ.(1) Max. Unit VIH Input High Voltage Guaranteed Logic High Level 2.0 — — 2.0 — — V VIL Input Low Voltage Guaranteed Logic Low Level — — 0.8 — — 0.8 V |ILI| Input Leakage Current VCC = Max., VIN = 0 to VCC — — 10 — — 10 µA |ILO| Output Leakage Current VCC = Max., OE = 2.0V — — 10 — — 10 µA VOUT = 0 to VCC ICC Operating Power Supply Current VCC = Max., Outputs Disabled — 40 80 — 40 100 mA f = 10MHz(2) ICCQ1 Quiescent Power Supply Current VIN ≥ VIH, VIN ≤ VIL — 20 40 — 20 50 mA ICCQ2 Quiescent Power Supply Current VIN ≥ VCC – 0.2V, VIN ≤ 0.2V — 4 20 — 4 25 mA ICC/f (2,3) Increase in Power Supply VCC = Max., Outputs Disabled — — 4 — — 6 mA/ Current MHz VOH Output HIGH Voltage VCC = Min., IOH = –2.0mA 2.4 — — 2.4 — — V VOL(4) Output LOW Voltage VCC = Min., IOL = 8mA — — 0.4 — — 0.4 V IOS Output Short Circuit Current VCC = Max., VO = GND -20 — -120 -20 — -120 mA NOTES: 2580 tbl 03 1. Typical implies VCC = 5V and TA = +25°C. 2. ICC is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range: ICC = 80+ 4(f –10)mA; for the military range, ICC = 100 + 6(f –10). f = operating frequency in MHz, f = 1/tMUC for IDT7216 and f = 1/tMC for IDT7217. 3. For frequencies greater than 10MHz, guaranteed by design, not production tested. 4. IOL = 4mA for tMC >65ns. 11.3 6 IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS COMMERCIAL (VCC = 5V ± 10%, TA = 0° to +70°C) 7216L16 (5) 7216L20 7216L25 7216L35 7217L16 7217L20 7217L25 7217L35 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit tMUC Unclocked Multiply Time(4) 2 25 2 30 2 38 2 55 ns tMC Clocked Multiply Time(4) 2 16 2 20 2 25 2 35 ns tS X, Y, RND Set-up Time 10 — 11 — 12 — 12 — ns tH X, Y, RND Hold Time 1 — 1 — 2 — 3 — ns tPWH Clock Pulse Width High 7 — 9 — 10 — 10 — ns tPWL Clock Pulse Width Low 7 — 9 — 10 — 10 — ns tPDSEL MSPSEL to Product Out(4) 2 15 2 18 2 20 2 25 ns tPDP Output Clock to P (4) 2 15 2 18 2 20 2 25 ns tPDY Output Clock to Y (4) 2 15 2 18 2 20 2 25 ns tENA 3-State Enable Time — 15 — 18 — 20 — 25 ns tDIS 3-State Disable Time(2) — 15 — 18 — 20 — 22 ns tS Clock Enable Set-up Time (IDT7217 only) 9 — 10 — 10 — 10 — ns tH Clock Enable Hold Time (IDT7217 only) 0 — 0 — 2 — 3 — ns tHCL Clock Low Hold Time CLKXY 0 — 0 — 0 — 0 — ns Relative to CLKML (IDT7216 only)(1,3) 7216L45 7216L55 7216L65 7217L45 7217L55 7217L65 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tMUC Unclocked Multiply Time(4) 2 65 2 75 2 85 ns tMC Clocked Multiply Time(4) 2 45 2 55 2 65 ns tS X, Y, RND Set-up Time 15 — 20 — 20 — ns tH X, Y, RND Hold Time 3 — 3 — 3 — ns tPWH Clock Pulse Width High 15 — 15 — 15 — ns tPWL Clock Pulse Width Low 15 — 20 — 20 — ns tPDSEL MSPSEL to Product Out(4) 2 25 2 25 2 30 ns tPDP Output Clock to P (4) 2 25 2 30 2 30 ns tPDY Output Clock to Y (4) 2 25 2 30 2 30 ns tENA 3-State Enable Time — 25 — 30 — 35 ns tDIS 3-State Disable Time(2) — 22 — 25 — 25 ns tS Clock Enable Set-up Time (IDT7217 only) 10 — 10 — 10 — ns tH Clock Enable Hold Time (IDT7217 only) 3 — 3 — 3 — ns tHCL Clock Low Hold Time CLKXY Relative to CLKML 0 — 0 — 0 — ns (IDT7216 only) (1,3) NOTES: 2580 tbl 06 1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been clocked. 2. Transition is measured ±500mV from steady state voltage. 3. Guaranteed by design, not production tested. 4. Minimum propagation delay times are guaranteed, not production tested. 5. This speed is available in PGA and PLCC packages only. 11.3 7 IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS MILITARY (VCC = 5V ± 10%, TA = –55° to +125°C) 7216L20 (5) 7216L25 7216L30 7216L40 7217L20 7217L25 7217L30 7217L40 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit tMUC Unclocked Multiply Time(4) 2 30 2 38 2 43 2 60 ns tMC Clocked Multiply Time(4) 2 30 2 25 2 30 2 40 ns tS X, Y, RND Set-up Time 11 — 12 — 12 — 15 — ns tH X, Y, RND Hold Time 1 — 2 — 2 — 3 — ns tPWH Clock Pulse Width High 9 — 10 — 10 — 15 — ns tPWL Clock Pulse Width Low 9 — 10 — 10 — 15 — ns tPDSEL MSPSEL to Product Out(4) 2 18 2 20 2 20 2 25 ns tPDP Output Clock to P (4) 2 18 2 20 2 20 2 25 ns tPDY Output Clock to Y (4) 2 18 2 20 2 20 2 25 ns tENA 3-State Enable Time — 18 — 20 — 20 — 25 ns tDIS 3-State Disable Time(2) — 20 — 22 — 22 — 25 ns tS Clock Enable Set-up Time (IDT7217 only) 10 — 10 — 10 — 12 — ns tH Clock Enable Hold Time (IDT7217 only) 0 — 2 — 2 — 3 — ns tHCL Clock Low Hold Time CLKXY Relative to 0 — 0 — 0 — 0 — ns CLKML (IDT7216 only)(1,3) 7216L55 7216L65 7216L75 7217L55 7217L65 7217L75 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tMUC Unclocked Multiply Time(4) 2 75 2 85 2 95 ns tMC Clocked Multiply Time(4) 2 55 2 65 2 75 ns tS X, Y, RND Set-up Time 20 — 25 — 25 — ns tH X, Y, RND Hold Time 3 — 3 — 3 — ns tPWH Clock Pulse Width High 15 — 15 — 15 — ns tPWL Clock Pulse Width Low 15 — 15 — 15 — ns tPDSEL MSPSEL to Product Out(4) 2 30 2 35 2 35 ns tPDP Output Clock to P (4) 2 30 2 30 2 35 ns tPDY Output Clock to Y (4) 2 30 2 30 2 35 ns tENA 3-State Enable Time — 25 — 35 — 40 ns tDIS 3-State Disable Time(2) — 25 — 25 — 25 ns tS Clock Enable Set-up Time (IDT7217 only) 15 — 15 — 15 — ns tH Clock Enable Hold Time (IDT7217 only) 3 — 3 — 3 — ns tHCL Clock Low Hold Time CLKXY Relative to CLKML 0 — 0 — 0 — ns (IDT7216 only) (1,3) NOTES: 2580 tbl 07 1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been clocked. 2. Transition is measured ±500mV from steady state voltage. 3. Guaranteed by design, not production tested. 4. Minimum propagation delay times are guaranteed, not production tested. 5. This speed is available in PGA and Flatpack packages only. 11.3 8 IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS MILITARY AND COMMERCIAL TEMPERATURE RANGES tPWH tHCL CLKX CLKY tS tH tPWL INPUT X1, Y1, RND tMC CLKM CLKL tPDY OUTPUT Y CLKM CLKL tPDSEL MSPSEL tPDP OUTPUT P tMUC 2580 drw 13 Figure 4. IDT7216 Timing Diagram tPWH CLK tS tH tPWL ENX ENY tS tH X1, Y1, RND tS tH ENP tMC tPDY OUTPUT Y tPDSEL MSPSEL tPDP OUTPUT P tMUC 2580 drw 14 Figure 5. IDT7217 Timing Diagram 11.3 9 BINARY POINT X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 SIGNAL 0 –1 –2 DIGITAL VALUE IDT7216L, IDT7217L –2 2 2 2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2 –14 2 –15 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 SIGNAL X 0 –1 –2 –2 2 2 2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2 –14 2 –15 DIGITAL VALUE P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 SIGNAL *= 16 x 16 PARALLEL CMOS MULTIPLIERS 0 –1 –2 DIGITAL VALUE –2 2 2 2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2 –14 2 –15 –2 0 2 –16 2 –17 2 –18 2 –19 2 –20 2 –21 2 –22 2 –23 2–24 2–25 2–26 2 –27 2 –28 2 –29 2 –30 MSP LSP FA = 0 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 SIGNAL = 1 0 DIGITAL VALUE –2 2 2 –1 2 –2 2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2 –14 2 –15 2 –16 2 –17 2 –18 2 –19 2 –20 2–21 2 –22 2 –23 2–24 2 –25 2–26 2 –27 2 –28 2 –29 2 –30 MSP LSP FA = 1 Figure 6. Fractional Two’s Complement Notation 2580 drw 16 11.3 BINARY POINT X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 SIGNAL –3 –8 –9 –11 –15 2–1 2–2 2 2–4 2–5 2–6 2–7 2 2 2–10 2 2–12 2–13 2–14 2 2–16 DIGITAL VALUE Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 SIGNAL X –3 –8 –9 –11 –15 2–1 2–2 2 2–4 2–5 2–6 2–7 2 2 2–10 2 2–12 2–13 2–14 2 2–16 DIGITAL VALUE P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 SIGNAL = –1 –2 –3 –6 –8 –9 –11 –24 –26 –27 DIGITAL VALUE –2 2 2 2–4 2–5 2 2–7 2 2 2–10 2 2–12 2–13 2–14 2–15 2–16 2–17 2–18 2–19 2–20 2–21 2–22 2–23 2 2–25 2 2 2–28 2–29 2–30 2–31 2–32 MSP LSP FA = 1 MANDATORY Figure 7. Fractional Unsigned Magnitude Notation 2580 drw17 10 MILITARY AND COMMERCIAL TEMPERATURE RANGES BINARY POINT X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 SIGNAL (TWO'S COMPLEMENT) -2 0 2 –1 2 –2 2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2 –14 2 –15 DIGITAL VALUE IDT7216L, IDT7217L Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 SIGNAL X (UNSIGNED MAGNITUDE) 2 –1 2 –2 2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2–14 2 –15 2 –16 DIGITAL VALUE P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 SIGNAL = 16 x 16 PARALLEL CMOS MULTIPLIERS 0 –1 –2 –2 2 2 2 –3 2 –4 2 –5 2 –6 2 –7 2 –8 2 –9 2–10 2–11 2 –12 2 –13 2 –14 2 –15 2 –16 2 –17 2 –18 2 –19 2 –20 2 –21 2 –22 2 –23 2–24 2–25 2–26 2 –27 2 –28 2 –29 2 –30 2 –31 DIGITAL VALUE FA = 1 MSP LSP MANDATORY Figure 8. Fractional Mixed Mode Notation 2580 drw 18 BINARY POINT 11.3 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 SIGNAL 15 14 13 11 9 8 5 0 –2 2 2 212 2 210 2 2 27 26 2 24 23 22 21 2 DIGITAL VALUE Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 SIGNAL X 14 13 11 8 5 2 0 –215 2 2 2 12 2 2 10 2 9 2 27 26 2 24 23 2 21 2 DIGITAL VALUE P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 SIGNAL *= 30 29 27 22 21 20 12 10 9 4 3 1 0 DIGITAL VALUE –2 2 228 2 226 225 224 223 2 2 2 219 218 217 216 215 –230 214 213 2 211 2 2 28 27 26 25 2 2 22 2 2 MSP LSP FA = 0 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 SIGNAL = 31 29 22 21 20 18 12 10 9 4 3 1 0 DIGITAL VALUE –2 230 2 228 227 226 225 224 223 2 2 2 219 2 217 216 215 214 213 2 211 2 2 28 27 26 25 2 2 22 2 2 MSP LSP FA = 1 Figure 9. Integer Two’s Complement Notation 2580 drw 19 11 * In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000 . . . 0 with 1,000.0 yielding an erroneous 30 MILITARY AND COMMERCIAL TEMPERATURE RANGES product of –1 in the fraction case and –2 in the integer case. BINARY POINT IDT7216L, IDT7217L X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 SIGNAL 15 14 11 10 7 5 3 2 2 2 213 212 2 2 29 28 2 26 2 24 2 2 21 20 DIGITAL VALUE Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 SIGNAL X 7 5 3 2 215 2 14 2 13 2 12 2 11 2 10 29 28 2 26 2 24 2 2 21 20 DIGITAL VALUE 16 x 16 PARALLEL CMOS MULTIPLIERS P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 SIGNAL 29 28 25 23 22 20 10 9 8 6 5 3 2 DIGITAL VALUE 231 230 2 2 227 226 2 224 2 2 221 2 219 218 217 216 215 214 213 212 211 2 2 2 27 2 2 24 2 2 21 20 MSB LSP FA = 1 MANDATORY Figure 10. Integer Unsigned Magnitude Notation 2580 drw 20 11.3 BINARY POINT X9 X7 X6 X2 X1 SIGNAL X15 X14 X13 X12 X11 X10 X8 X5 X4 X3 X0 (TWO'S COMPLEMENT) 7 5 3 2 –215 2 14 2 13 2 12 2 11 2 10 29 28 2 26 2 24 2 2 21 20 DIGITAL VALUE Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 SIGNAL Y15 Y14 Y13 Y12 Y11 Y10 X (UNSIGNED MAGNITUDE) 15 14 11 10 7 5 3 2 2 2 213 212 2 2 29 28 2 26 2 24 2 2 21 20 DIGITAL VALUE P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 SIGNAL 31 8 6 5 3 2 DIGITAL VALUE –2 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 23 2 22 221 220 2 19 218 2 17 2 16 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 27 2 2 24 2 2 21 20 MSB LSP FA = 1 MANDATORY Figure 11. Integer Mixed Mode Notation 2580 drw 21 12 MILITARY AND COMMERCIAL TEMPERATURE RANGES IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS MILITARY AND COMMERCIAL TEMPERATURE RANGES AC TEST CONDITIONS Input Pulse Levels GND to 3.0V VCC 7.0V Input Rise/Fall Times 3ns 500Ω Input Timing Reference Levels 1.5V V OUT Output Reference Levels 1.5V VIN Pulse Output Load See Figure 1 Generator D.U.T. 2580 tbl 08 50pF SWITCH POSITION 500Ω RT CL Test Switch Disable Low Closed Enable Low All Other Tests Open Figure 12. AC Test Load Circuit DEFINITIONS: 2580 tbl 09 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. VCC ESD PROTECTION I OH IIH OUTPUTS INPUTS IIL R I OL Figure 13. Input Interface Circuit Figure 14. Output Interface Circuit ORDERING INFORMATION IDT XXXX X X X X Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0°C to +70°C) B Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B C Topbraze DIP J Plastic Leaded Chip Carrier F Flatpack G Pin Grid Array 16 20 20 25 25 30 Commercial (tMC) Military (tMC) 35 40 45 55 55 65 65 75 L Low Power 7216 16 x 16 Multiplier 7217 2580 drw 22 11.3 13 This datasheet has been downloaded from: www.DatasheetCatalog.com Datasheets for electronic components.