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Source PDF: /mnt/main/jmc-storage/docs/Hardware/Intel/UPI-C42,UPI-L42 UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER.pdf Like all conversions the text below should be fully readable as UTF-8 unicode text. --------------------------------------------------------------- UPI-C42 UPI-L42 UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER Y Pin Software and Architecturally Y One 8-Bit Status and Two Data Compatible with all UPI-41 and UPI-42 Registers for Asynchronous Slave-to- Products Master Interface Y Low Voltage Operation with the UPI- Y Fully Compatible with all Intel and Most L42 Other Microprocessor Families Full 3 3V Support Y Interchangeable ROM and OTP EPROM Y Hardware A20 Gate Support Versions Y Suspend Power Down Mode Y Expandable I O Y Security Bit Code Protection Support Y Sync Mode Available Y 8-Bit CPU plus ROM OTP EPROM RAM Y Over 90 Instructions 70% Single Byte I O Timer Counter and Clock in a Y Quick Pulse Programming Algorithm Single Package Fast OTP Programming Y 4096 x 8 ROM OTP 256 x 8 RAM 8-Bit Y Available in 40-Lead Plastic 44-Lead Timer Counter 18 Programmable I O Plastic Leaded Chip Carrier and Pins 44-Lead Quad Flat Pack Packages Y DMA Interrupt or Polled Operation (See Packaging Spec Order 240800 Package Type P N and S) Supported The UPI-C42 is an enhanced CHMOS version of the industry standard Intel UPI-42 family It is fabricated on Intel’s CHMOS III-E process The UPI-C42 is pin software and architecturally compatible with the NMOS UPI family The UPI-C42 has all of the same features of the NMOS family plus a larger user programmable memory array (4K) hardware A20 gate support and lower power consumption inherent to a CHMOS product The UPI-L42 offers the same functionality and socket compatibility as the UPI-C42 as well as providing low voltage 3 3V operation The UPI-C42 is essentially a ‘‘slave’’ microcontroller or a microcontroller with a slave interface included on the chip Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS Modules and iAPX family as well as other 8- 16- and 32-bit systems To allow full user flexibility the program memory is available in ROM and One-Time Programmable EPROM (OTP) 290414 – 1 Figure 1 DIP Pin 290414 – 3 290414 – 2 Configuration Figure 2 PLCC Pin Configuration Figure 3 QFP Pin Configuration Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1996 December 1995 Order Number 290414-003 UPI-C42 UPI-L42 Table 1 Pin Description DIP PLCC QFP Symbol Pin Pin Pin Type Name and Function No No No TEST 0 1 2 18 I TEST INPUTS Input pins which can be directly tested using conditional TEST 1 39 43 16 branch instructions FREQUENCY REFERENCE TEST 1 (T1) functions as the event timer input (under software control) TEST 0 (T0) is a multi-function pin used during PROM programming and ROM EPROM verification during Sync Mode to reset the instruction state to S1 and synchronize the internal clock to PH1 XTAL 1 2 3 19 O OUTPUT Output from the oscillator amplifier XTAL 2 3 4 20 I INPUT Input to the oscillator amplifier and internal clock generator circuits RESET 4 5 22 I RESET Input used to reset status flip-flops set the program counter to zero and force the UPI-C42 from the suspend power down mode RESET is also used during EPROM programming and verification SS 5 6 23 I SINGLE STEP Single step input used in conjunction with the SYNC output to step the program through each instruction (EPROM) This should be tied to a 5V when not used This pin is also used to put the device in Sync Mode by applying 12 5V to it CS 6 7 24 I CHIP SELECT Chip select input used to select one UPI microcomputer out of several connected to a common data bus EA 7 8 25 I EXTERNAL ACCESS External access input which allows emulation testing and ROM EPROM verification This pin should be tied low if unused RD 8 9 26 I READ I O read input which enables the master CPU to read data and status words from the OUTPUT DATA BUS BUFFER or status register A0 9 10 27 I COMMAND DATA SELECT Address Input used by the master processor to indicate whether byte transfer is data (A0 e 0 F1 is reset) or command (A0 e 1 F1 is set) A0 e 0 during program and verify operations WR 10 11 28 I WRITE I O write input which enables the master CPU to write data and command words to the UPI INPUT DATA BUS BUFFER SYNC 11 13 29 O OUTPUT CLOCK Output signal which occurs once per UPI instruction cycle SYNC can be used as a strobe for external circuitry it is also used to synchronize single step operation D0 – D7 12– 19 14– 21 30– 37 I O DATA BUS Three-state bidirectional DATA BUS BUFFER lines used to (BUS) interface the UPI microcomputer to an 8-bit master system data bus P10 – P17 27– 34 30– 33 2 – 10 I O PORT 1 8-bit PORT 1 quasi-bidirectional I O lines P10 –P17 access the 35– 38 signature row and security bit 2 UPI-C42 UPI-L42 Table 1 Pin Description (Continued) DIP PLCC QFP Symbol Pin Pin Pin Type Name and Function No No No P20 – P27 21– 24 24– 27 39– 42 I O PORT 2 8-bit PORT 2 quasi-bidirectional I O lines The lower 4 bits 35– 38 39– 42 11 13– 15 (P20 –P23) interface directly to the 8243 I O expander device and contain address and data information during PORT 4 – 7 access P21 can be programmed to provide hardware A20 gate support The upper 4 bits (P24 –P27) can be programmed to provide interrupt Request and DMA Handshake capability Software control can configure P24 as Output Buffer Full (OBF) interrupt P25 as Input Buffer Full (IBF) interrupt P26 as DMA Request (DRQ) and P27 as DMA ACKnowledge (DACK) PROG 25 28 43 I O PROGRAM Multifunction pin used as the program pulse input during PROM programming During I O expander access the PROG pin acts as an address data strobe to the 8243 This pin should be tied high if unused VCC 40 44 17 POWER a 5V main power supply pin VDD 26 29 1 POWER a 5V during normal operation a 12 75V during programming operation Low power standby supply pin VSS 20 22 38 GROUND Circuit ground potential 290414 – 4 Figure 4 Block Diagram 3 UPI-C42 UPI-L42 UPI-C42 L42 PRODUCT SELECTION GUIDE UPI-C42 Low power CHMOS version of the UPI-42 Device Package ROM OTP Comments 80C42 N PS 4K ROM Device 82C42PC N P S Phoenix MultiKey 42 firmware PS 2 style mouse support 82C42PD N P S Phoenix MultiKey 42L firmware KBC and SCC for portable apps 82C42PE N P S Phoenix MultiKey 42G firmware Energy Efficient KBC solution 87C42 N P S 4K One Time Programmable Version UPI-L42 The low voltage 3 3V version of the UPI-C42 Device Package ROM OTP Comments 80L42 N PS 4K ROM Device 82L42PC N P S Phoenix MultiKey 42 firmware PS 2 style mouse support 82L42PD N P S Phoenix MultiKey 42L firmware KBC and SCC for portable apps 87L42 N P S 4K One Time Programmable Version N e 44 lead PLCC P e 40 lead PDIP S e 44 lead QFP D e 40 lead CERDIP KBC e Key Board Control SCC e Scan Code Control THE INTEL 82C42 The 82C42PC provides a low powered solution for industry standard keyboard and PS 2 style mouse As shown in the UPI-C42 product matrix the UPI- control The 82C42PD provides a cost effective C42 is offered as a pre-programmed 80C42 with var- means for keyboard and scan code control for note- ious versions of MultiKey 42 keyboard controller book platforms The 82C42PE allows a quick time to firmware developed by Phoenix Technologies Ltd market low cost solution for energy efficient desk- top designs 4 UPI-C42 UPI-L42 UPI-42 COMPATIBLE FEATURES 4 P24 and P25 are port pins or Buffer Flag pins which can be used to interrupt a master proces- 1 Two Data Bus Buffers one for input and one for sor These pins default to port pins on Reset output This allows a much cleaner Master Slave If the ‘‘EN FLAGS’’ instruction has been execut- protocol ed P24 becomes the OBF (Output Buffer Full) pin A ‘‘1’’ written to P24 enables the OBF pin (the pin outputs the OBF Status Bit) A ‘‘0’’ written to P24 disables the OBF pin (the pin remains low) This pin can be used to indicate that valid data is available from the UPI (in Output Data Bus Buff- er) If ‘‘EN FLAGS’’ has been executed P25 be- comes the IBF (Input Buffer Full) pin A ‘‘1’’ writ- ten to P25 enables the IBF pin (the pin outputs the inverse of the IBF Status Bit A ‘‘0’’ written to P25 disables the IBF pin (the pin remains low) This pin can be used to indicate that the UPI is 290414 – 5 ready for data 2 8 Bits of Status Data Bus Buffer Interrupt Capability ST7 ST6 ST5 ST4 F1 F0 IBF OBF D7 D6 D5 D4 D3 D2 D1 D0 ST4 –ST7 are user definable status bits These bits are defined by the ‘‘MOV STS A’’ single byte single cycle instruction Bits 4–7 of the acccumulator are moved to bits 4–7 of the status register Bits 0–3 of the status register are not affected 290414 – 7 MOV STS A Op Code 90H 1 0 0 1 0 0 0 0 EN FLAGS Op Code 0F5H D7 D0 1 1 1 1 0 1 0 1 3 RD and WR are edge triggered IBF OBF F1 and D7 D0 INT change internally after the trailing edge of RD or WR 5 P26 and P27 are port pins or DMA handshake pins for use with a DMA controller These pins During the time that the host CPU is reading the default to port pins on Reset status register the UPI is prevented from updat- ing this register or is ‘locked out ’ If the ‘‘EN DMA’’ instruction has been executed P26 becomes the DRQ (DMA Request) pin A ‘‘1’’ written to P26 causes a DMA request (DRQ is activated) DRQ is deactivated by DACK  RD DACK  WR or execution of the ‘‘EN DMA’’ in- struction 290414 – 6 DMA Handshake Capability 290414 – 8 5 UPI-C42 UPI-L42 If ‘‘EN DMA’’ has been executed P27 becomes PROGRAM MEMORY BANK SWITCH the DACK (DMA ACKnowledge) pin This pin acts as a chip select input for the Data Bus Buffer The switching of 2K program memory banks is ac- registers during DMA transfers complished by directly setting or resetting the most significant bit of the program counter (bit 11) see EN DMA Op Code 0E5H Figure 5 Bit 11 is not altered by normal increment- 1 1 1 0 0 1 0 1 ing of the program counter but is loaded with the contents of a special flip-flop each time a JMP or D7 D0 CALL instruction is executed This special flip-flop is 6 When EA is enabled on the UPI the program set by executing an SEL PMB1 instruction and reset counter is placed on Port 1 and the lower four by SEL PMB0 Therefore the SEL PMB instruction bits of Port 2 (MSB e P23 LSB e P10) On the may be executed at any time prior to the actual bank UPI this information is multiplexed with PORT switch which occurs during the next branch instruc- DATA (see port timing diagrams at end of this tion encountered Since all twelve bits of the pro- data sheet) gram counter including bit 11 are stored in the 7 The UPI-C42 supports the Quick Pulse Program- stack when a Call is executed the user may jump to ming Algorithm but can also be programmed subroutines across the 2K boundary and the proper with the Intelligent Programming Algorithm (See PC will be restored upon return However the bank the Programming Section ) switch flip-flop will not be altered on return UPI-C42 FEATURES Programmable Memory Size Increase The user programmable memory on the UPI-C42 will be increased from the 2K available in the NMOS product by 2X to 4K The larger user programmable memory array will allow the user to develop more complex peripheral control micro-code P2 3 (port 2 bit 3) has been designated as the extra address pin required to support the programming of the extra 2K of user programmable memory 290414 – 30 The new instruction SEL PMB1 (73h) allows for ac- Figure 5 Program Counter cess to the upper 2K bank (locations 2048–4095) The additional memory is completely transparent to users not wishing to take advantage of the extra INTERRUPT ROUTINES memory space No new commands are required to access the lower 2K bytes The SEL PMB0 (63h) Interrupts always vector the program counter to lo- has also been added to the UPI-C42 instruction set cation 3 or 7 in the first 2K bank and bit 11 of the to allow for switching between memory banks program counter is held at ‘‘0’’ during the interrupt service routine The end of the service routine is sig- naled by the execution of an RETR instruction Inter- rupt service routines should therefore be contained Extended Memory Program entirely in the lower 2K words of program memory Addressing (Beyond 2K) The execution of a SEL PMB0 or SEL PMB1 instruc- For programs of 2K words or less the UPI-C42 ad- tion within an interrupt routine is not recommended dresses program memory in the conventional man- since it will not alter PC11 while in the routine but ner Addresses beyond 2047 can be reached by ex- will change the internal flip-flop ecuting a program memory bank switch instruction (SEL PMB0 SEL PMB1) followed by a branch in- struction (JMP or CALL) The bank switch feature Hardware A20 Gate Support extends the range of branch instructions beyond This feature has been provided to enhance the per- their normal 2K range and at the same time prevents formance of the UPI-C42 when being used in a key- the user from inadvertently crossing the 2K boundary board controller application The UPI-C42 design has included on chip logic to support a hardware GATEA20 feature which eliminates the need to pro- vide firmware to process A20 command sequences 6 UPI-C42 UPI-L42 thereby providing additional user programmable SUSPEND memory space This feature is enabled by the A20EN instruction and remains enabled until the de- The execution of the suspend instruction (82h or vice is reset It is important to note that the execu- E2h) causes the UPI-C42 to enter the suspend tion of the A20EN instruction redefines Port 2 bit 1 mode In this mode of operation the oscillator is not as a pure output pin with read only characteristics running and the internal CPU operation is stopped The state of this pin can be modified only through a The UPI-C42 consumes s 40 mA in the suspend valid ‘‘D1’’ command sequence (see Table 1) Once mode This mode can only be exited by RESET enabled the A20 logic will process a ‘‘D1’’ com- CPU operation will begin from PC e 000h when the mand sequence (write to output port) by setting re- UPI-C42 exits from the suspend power down mode setting the A20 bit on port 2 bit 1 (P2 1) without requiring service from the internal CPU The host can directly control the status of the A20 bit At no Suspend Mode Summary time during this host interface transaction will the IBF flag in the status register be activated Table 1  Oscillator Not Running gives several possible GATEA20 command data se-  CPU Operation Stopped quences and UPI-C42 responses  Ports Tristated with Weak ( E 2–10 mA) Pull-Up Table 1 D1 Command Sequences  Micropower Mode (ICC s 40 mA) A0 R W DB Pins IBF A20 Comments  This mode is exited by RESET 1 W D1h 0 n(1) Set A20 Sequence 0 W DFh 0 1 Only DB1 Is Processed 1 W FFH(2) 0 n 1 W D1h 0 n Clear A20 Sequence 0 W DDh 0 0 1 W FFh 0 n 1 W D1h 0 n Double Trigger Set 1 W D1h 0 n Sequence 0 W DFh 0 1 1 W FFh 0 n 1 W D1h 0 n Invalid Sequence 1 W XXh(3) 1 n No Change in State 0 W DDh 1 n of A20 Bit NOTES 1 Indicates that P2 1 remains at the previous logic level 2 Only FFh commands in a valid A20 sequence have no effect on IBF An FFh issued at any other time will activate IBF 3 Any command except D1 The above sequences assume that the GATEA20 logic has been enabled via the A20EN instruction As noted only the value on DB 1 (data bus bit 1) is processed This bit will be directly passed through to P2 1 (port 2 bit 1) 7 UPI-C42 UPI-L42 Table 2 covers all suspend mode pin states In addi- NEW UPI-C42 INSTRUCTIONS tion to the suspend power down mode the UPI-C42 will also support the NMOS power down mode as The UPI-C42 will support several new instructions to outlined in Chapter 4 of the UPI-42AH users manual allow for the use of new C42 features These in- structions are not necessary to the user who does Table 2 Suspend Mode Pin States not wish to take advantage of any new C42 function- ality The C42 will be completely compatible with all Pins Suspend current NMOS code applications In order to use Ports 1 and 2 new features however some code modifications will Outputs Tristate be necessary All new instructions can easily be in- Inputs Weak Pull-Up serted into existing code by use of the ASM-48 mac- Disabled ro facility as shown in the following example DBB(1) Macname MACRO Outputs Normal DB 63H Inputs Normal ENDM System Control Disabled (RD WR New Instructions CS A0) The following is a list of additions to the UPI-42 in- Reset Enabled struction set These instructions apply only to the Crystal Osc Disabled UPI-C42 These instructions must be added to exist- (XTAL1 XTAL2) ing code in order to use any new functionality Test 0 Test 1 Disabled SEL PMB0 Select Program Memory Bank 0 Prog High OPCODE 0110 0011 (63h) Sync High PC Bit 11 is set to zero on next JMP or CALL instruc- EA Disabled tion All references to program memory fall within No Pull-Up the range of 0 – 2047 (0 – 7FFh) SS Disabled Weak Pull-Up SEL PMB1 Select Program Memory Bank 1 ICC k 40 mA OPCODE 0111 0011 (73h) NOTES PC Bit 11 is set to one on next JMP or CALL instruc- 1 DBB outputs are Tristate unless CS and RD are ac- tion All references to program memory fall within tive DBB inputs are disabled unless CS and WR are active the range of 2048 – 4095 (800h – FFFh) 2 A ‘‘disabled’’ input will not cause current to be drawn regardless of input level (within the supply range) ENA20 Enables Auto A20 hardware 3 Weak pull-ups have current capability of typically 5 mA OPCODE 0011 0011 (33h) Enables on chip logic to support Hardware A20 Gate feature Will remain enabled until device is reset 8 UPI-C42 UPI-L42 This circuitry gives the host direct control of port 2 bit 1 (P2 1) without intervention by the internal CPU Pin Function When this opcode is executed P2 1 becomes a ded- XTAL 2 Clock Input icated output pin The status of this pin is read-able but can only be altered through a valid ‘‘D1’’ com- Reset Initialization and Address Latching mand sequence (see Table 1) Test 0 Selection of Program or Verify Mode SUSPEND Invoke Suspend Power Down Mode EA Activation of Program Verify Signature Row Security Bit Modes OPCODE 1000 0010 (82h) or 1110 0010 BUS Address and Data Input (E2h) Data Output During Verify Enables device to enter micro power mode In this P20–23 Address Input mode the external oscillator is off CPU operation is stopped and the Port pins are tristated This mode VDD Programming Power Supply can only be exited via a RESET signal PROG Program Pulse Input WARNING PROGRAMMING AND VERIFYING THE An attempt to program a missocketed UPI-C42 will result in UPI-C42 severe damage to the part An indication of a properly socketed part is the appearance of the SYNC clock output The UPI-C42 programming will differ from the NMOS The lack of this clock may be used to disable the program- device in three ways First the C42 will have a 4K mer user programmable array The UPI-C42 will also be programmed using the Intel Quick-Pulse Program- The Program Verify sequence is ming Algorithm Finally port 2 bit three (P2 3) will be 1 Insert 87C42 in programming socket used during program as the extra address pin re- 2 CS e 5V VCC e 5V VDD e 5V RESET e 0V quired to program the upper 2K bank of additional A0 e 0V TEST 0 e 5V clock applied or inter- memory None of these differences have any effect nal oscillator operating BUS floating PROG e on the full CHMOS to NMOS device compatibility 5V The extra memory is fully transparent to the user who does not need or want to use the extra memo- 3 TEST 0 e 0V (select program mode) ry space of the UPI-C42 4 EA e 12 75V (active program mode) 5 VCC e 6 25V (programming supply) In brief the programming process consists of acti- vating the program mode applying an address 6 VDD e 12 75V (programming power) latching the address applying data and applying a 7 Address applied to BUS and P20–23 programming pulse Each word is programmed com- 8 RESET e 5V (latch address) pletely before moving on to the next and is followed by a verification step The following is a list of the 9 Data applied to BUS pins used for programming and a description of their 10 PROG e 5V followed by one 100 ms pulse to functions 0V 11 TEST 0 e 5V (verify mode) 12 Read and verify data on BUS 13 TEST 0 e 0V 14 RESET e 0V and repeat from step 6 15 Programmer should be at conditions of step 1 when the 87C42 is removed from socket Please follow the Quick-Pulse Programming flow chart for proper programming procedure shown in Figure 6 9 UPI-C42 UPI-L42 flow chart of the Quick-Pulse Programming Algo- rithm is shown in Figure 6 The entire sequence of program pulses and byte verifications is performed at VCC e 6 25V and VDD e 12 75V When programming has been com- pleted all bytes should be compared to the original data with VCC e VDD e 5V A verify should be performed on the programmed bits to ensure that they have been correctly pro- grammed The verify is performed with T0 e 5V VDD e 5V EA e 12 75V SS e 5V PROG e 5V A0 e 0V and CS e 5V In addition to the Quick-Pulse Programming Algo- rithm the UPI-C42 OPT is also compatible with In- tel’s Inteligent Programming Algorithm which is used to program the NMOS UPI-42AH OTP devices The entire sequence of program pulses and byte verifications is performed at VCC e 6 25V and VDD e 12 75V When the inteligent Programming cycle has been completed all bytes should be com- pared to the original data with VCC e 5 0 VDD e 5V Verify A verify should be performed on the programmed bits to determine that they have been correctly pro- grammed The verify is performed with T0 e 5V VDD e 5V EA e 12 75V SS e 5V PROG e 5V A0 e 0V and CS e 5V SECURITY BIT The security bit is a single EPROM cell outside the EPROM array The user can program this bit with the appropriate access code and the normal program- ming procedure to inhibit any external access to the 290414 – 14 EPROM contents Thus the user’s resident program Figure 6 Quick-Pulse Programming Algorithm is protected There is no direct external access to this bit However the security byte in the signature row has the same address and can be used to check indirectly whether the security bit has been Quick-Pulse Programming Algorithm programmed or not The security bit has no effect on As previously stated the UPI-C42 will be pro- the signature mode so the security byte can always grammed using the Quick-Pulse Programming Algo- be examined rithm developed by Intel to substantially reduce the thorughput time in production programming SECURITY BIT PROGRAMMING The Quick-Pulse Programming Algorithm uses initial VERIFICATION pulses of 100 ms followed by a byte verification to determine when the address byte has been suc- cessfully programmed Up to 25 100 ms pulses per Programming byte are provided before a failure is recognized A a Read the security byte of the signature mode Make sure it is 00H 10 UPI-C42 UPI-L42 b Apply access code to appropriate inputs to put and will be present in the ROM and OTP ver- the device into security mode sions Location 10H contains the manufacturer c Apply high voltage to EA and VDD pins code For Intel it is 89H Location 11H contains the device code d Follow the programming procedure as per the Quick-Pulse Programming Algorithm with known The code is 43H and 42H for the 8042AH 80C42 data on the databus Not only the security bit but and OTP 8742AH 87C42 respectively The also the security byte of the signature row is pro- code is 44H for any device with the security bit grammed set by Intel e Verify that the security byte of the signature C User signature The user signature memory is mode contains the same data as appeared on implemented in the EPROM and consists of 2 the data bus (If DB0–DB7 e high the security bytes for the customer to program his own signa- byte will contain FFH ) ture code (for identification purposes and quick sorting of previously programmed materials) f Read two consecutive known bytes from the EPROM array and verify that the wrong data are D Test signature This memory is used to store retrieved in at least one verification If the testing information such as test data bin num- EPROM can still be read the security bit may ber etc (for use in quality and manufacturing have not been fully programmed though the se- control) curity byte in the signature mode has E Security byte This byte is used to check whether the security bit has been programmed (see the security bit section) Verification F UPI-C42 Intel Signature Applies only to CHMOS device Location 20H contains the man- Since the security bit address overlaps the address ufacturer code and location 21H contains the de- of the security byte of the signature mode it can be vice code The Intel UPI-C42 manufacturer’s used to check indirectly whether the security bit has code is 99H The device ID’s are 82H for the been programmed or not Therefore the security bit OTP version and 83H for the ROM version The verification is a mere read operation of the security device ID’s are the same for the UPI-L42 byte of the signature row (0FFH e security bit pro- grammed 00H e security bit unprogrammed) Note The signature mode can be accessed by setting that during the security bit programming the reading P10 e 0 P11 – P17 e 1 and then following the pro- of the security byte does not necessarily indicate gramming and or verification procedures The loca- that the security bit has been successfully pro- tion of the various address partitions are as shown in grammed Thus it is recommended that two consec- Table 3 utive known bytes in the EPROM array be read and the wrong data should be read at least once be- cause it is highly improbable that random data coin- cides with the correct ones twice SYNC MODE The Sync Mode is provided to ease the design of multiple controller circuits by allowing the designer SIGNATURE MODE to force the device into known phase and state time The Sync Mode may also be utilized by automatic The UPI-C42 has an additional 64 bytes of EPROM test equipment (ATE) for quick easy and efficient available for Intel and user signatures and miscella- synchronizing between the tester and the DUT (de- neous purposes The 64 bytes are partitioned as fol- vice under test) lows A Test code checksum This can accommodate Sync Mode is enabled when SS pin is raised to high up to 25 bytes of code for testing the internal voltage level of a 12 volts To begin synchroniza- nodes that are not testable by executing from the tion T0 is raised to 5 volts at least four clock cycles external memory The test code checksum is after SS T0 must be high for at least four X2 clock present on ROMs and OTPs cycles to fully reset the prescaler and time state B Intel signature This allows the programmer to generators T0 may then be brought down during read from the UPI-41AH 42AH C42 the manu- low state of X2 Two clock cycles later with the ris- facturer of the device and the exact product ing edge of X2 the device enters into Time State 1 name It facilitates automatic device identification Phase 1 SS is then brought down to 5 volts 4 clocks later after T0 RESET is allowed to go high 5 tCY (75 clocks) later for normal execution of code 11 UPI-C42 UPI-L42 Table 3 Signature Mode Table Device No of Address Type Bytes Test Code Checksum 0 0FH ROM OTP 25 16H 1EH Intel Signature 10H 11H ROM OTP 2 User Signature 12H 13H OTP 2 Test Signature 14H 15H ROM OTP 2 Security Byte 1FH or 3FH ROM OTP 2 UPI-C42 Intel Signature 20H 21H ROM OTP 2 User Defined UPI-C42 OTP EPROM Space 22H 3EH ROM OTP 30 ACCESS CODE The following table summarizes the access codes required to invoke the Sync Mode Signature Mode and the Security Bit respectively Also the programming and verification modes are included for comparison Access Code Control Signals Data Bus Modes Port 2 Port 1 T0 RST SS EA PROG VDD VCC 0 1 2 3 4 5 6 7 0 1 2 3 0 1 2 3 4 5 6 7 Programming 0 0 1 HV 1 VDDH VCC Address Addr a0 a1 X X X X X X Mode 0 1 1 HV STB VDDH VCC Data In Addr Verification 0 0 1 HV 1 VCC VCC Address Addr a0 a1 X X X X X X Mode 1 1 1 HV 1 VCC VCC Data Out Addr Sync Mode STB 0 HV 0 X VCC VCC X X X X X X X X X X X X X X X X X X X High Signature Prog 0 0 1 HV 1 VDDH VCC Addr (see Sig Mode Table) 0 0 0 0 1 1 1 1 X X 1 Mode 0 1 1 HV STB VDDH VCC Data In 0 0 0 Verify 0 0 1 HV 1 VCC VCC Addr (see Sig Mode Table) 0 0 0 1 1 1 HV 1 VCC VCC Data Out 0 0 0 Security Prog 0 0 1 HV 1 VDDH VCC Address 0 0 0 Bit Byte 0 1 1 HV STB VDDH VCC Data In 0 0 0 Verify 0 0 1 HV 1 VCC VCC Address 0 0 0 1 1 1 HV 1 VCC VCC Data Out 0 0 0 NOTE 1 a0 e 0 or 1 a1 e 0 or 1 a0 must e a1 12 UPI-C42 UPI-L42 SYNC MODE TIMING DIAGRAMS 290414 – 15 Minimum Specifications SYNC Operation Time tSYNC e 3 5 XTAL 2 Clock cycles Reset Time tRS e 4 tCY NOTE The rising and falling edges of T0 should occur during low state of XTAL 2 clock APPLICATIONS 290414 – 12 Figure 7 UPI-C42 Keyboard Controller 290414 – 9 Figure 8 8088-UPI-C42 Interface 13 UPI-C42 UPI-L42 APPLICATIONS (Continued) 290414 – 10 Figure 9 8048H-UPI-C42 Interface 290414 – 11 Figure 10 UPI-C42-8243 Keyboard Scanner 290414 – 13 Figure 11 UPI-C42 80-Column Matrix Printer Interface 14 UPI-C42 UPI-L42 ABSOLUTE MAXIMUM RATINGS NOTICE This is a production data sheet The specifi- cations are subject to change without notice Ambient Temperature Under Bias 0 C to a 70 C WARNING Stressing the device beyond the ‘‘Absolute Storage Temperature b 65 C to a 150 C Maximum Ratings’’ may cause permanent damage Voltage on Any Pin with These are stress ratings only Operation beyond the Respect to Ground b 0 5V to a 7V ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ Power Dissipation 15W may affect device reliability DC CHARACTERISTICS TA e 0 C to a 70 C VCC e VDD e a 5V g 10% a 3 3V g 10% UPI-L42 UPI-C42 UPI-L42 Symbol Parameter Units Notes Min Max Min Max VIL Input Low Voltage b0 5 08 b0 3 a0 8 V All Pins VIH Input High Voltage 20 VCC 20 VCC a 0 3 V (Except XTAL2 RESET) VIH1 Input High Voltage 35 VCC 20 VCC a 0 3 V (XTAL2 RESET) VOL Output Low Voltage (D0 –D7) 0 45 0 45 V IOL e 2 0 mA UPI-C42 IOL e 1 3 mA UPI-L42 VOL1 Output Low Voltage 0 45 0 45 V IOL e 1 6 mA UPI-C42 (P10P17 P20P27 Sync) IOL e 1 mA UPI-L42 VOL2 Output Low Voltage (PROG) 0 45 0 45 V IOL e 1 0 mA UPI-C42 IOL e 0 7 mA UPI-L42 VOH Output High Voltage (D0 –D7) 24 24 V IOH e b 400 mA UPI-C42 IOH e b 260 mA UPI-L42 VOH1 Output High Voltage 24 24 IOH e b 50 mA UPI-C42 (All Other Outputs) IOH e b 25 mA UPI-L42 IIL Input Leakage Current g 10 g 10 mA VSS s VIN s VCC (T0 T1 RD WR CS A0 EA) IOFL Output Leakage Current g 10 g 10 mA VSS a 0 45 s VOUT s VCC (D0 –D7 High Z State) ILI Low Input Load Current b 50 b 250 b 35 b 175 mA Port Pins (P10P17 P20P27) Min VIN e 2 4V Max VIN e 0 45V ILI1 Low Input Load Current b 40 b 40 mA VIN s VIL (RESET SS) IHI Port Sink Current VCC e 3 0V 50 mA (P10P17 P20P27) VIH e 5 0V IDD VDD Supply Current 4 25 mA 15 UPI-C42 UPI-L42 DC CHARACTERISTICS TA e 0 C to a 70 C VCC e VDD e a 5V g 10% a 3 3V g 10% UPI-L42 (Continued) UPI-C42 UPI-L42 Symbol Parameter Units Notes Min Max Min Max ICC a IDD Total Supply Current Active Mode 12 5 MHz 30 20 mA Typical 14 mA UPI-C42 9 mA UPI-L42 Suspend Mode 40 26 mA Osc Off(1 4) IDD Standby Power Down 5 35 mA NMOS Compatible Supply Current Power Down Mode IIH Input Leakage Current 100 100 mA VIN e VCC (P10 –P17 P20 –P27) CIN Input Capacitance 10 10 pF TA e 25 C (1) CIO I O Capacitance 20 20 pF TA e 25 C (1) NOTE 1 Sampled not 100% tested DC CHARACTERISTICS PROGRAMMING (UPI-C42 AND UPI-L42) TA e 25 C g 5 C VCC e 6 25V g 0 25V VDD e 12 75V g 0 25V Symbol Parameter Min Max Units VDDH VDD Program Voltage High Level 12 5 13 V(1) VDDL VDD Voltage Low Level 4 75 5 25 V VPH PROG Program Voltage High Level 20 55 V VPL PROG Voltage Low Level b0 5 08 V VEAH Input High Voltage for EA 12 0 13 0 V(2) VEAL EA Voltage Low Level b0 5 5 25 V IDD VDD High Voltage Supply Current 50 0 mA IEA EA High Voltage Supply Current 10 mA(4) NOTES 1 Voltages over 13V applied to pin VDD will permanently damage the device 2 VEAH must be applied to EA before VDDH and removed after VDDL 3 VCC must be applied simultaneously or before VDD and must be removed simultaneously or after VDD 4 Sampled not 100% tested 16 UPI-C42 UPI-L42 AC CHARACTERISTICS TA e 0 C to a 70 C VSS e 0V VCC e VDD e a 5V g 10% a 3 3V g 10% for the UPI-L42 NOTE All AC Characteristics apply to both the UPI-C42 and UPI-L42 DBB READ Symbol Parameter Min Max Units tAR CS A0 Setup to RDv 0 ns tRA CS A0 Hold After RDu 0 ns tRR RD Pulse Width 160 ns tAD CS A0 to Data Out Delay 130 ns tRD RDv to Data Out Delay 0 130 ns tDF RDu to Data Float Delay 85 ns DBB WRITE Symbol Parameter Min Max Units tAW CS A0 Setup to WRv 0 ns tWA CS A0 Hold After WRu 0 ns tWW WR Pulse Width 160 ns tDW Data Setup to WRu 130 ns tWD Data Hold After WRu 0 ns 17 UPI-C42 UPI-L42 AC CHARACTERISTICS TA e 0 C to a 70 C VSS e 0V VCC e VDD e a 5V g 10% a 3 3V g 10% for the UPI-L42 (Continued) CLOCK Symbol Parameter Min Max Units tCY UPI-C42 UPI-L42 Cycle Time 12 9 20 ms(1) tCYC UPI-C42 UPI-L42 Clock Period 80 613 ns tPWH Clock High Time 30 ns tPWL Clock Low Time 30 ns tR Clock Rise Time 10 ns tF Clock Fall Time 10 ns NOTE 1 tCY e 15 f(XTAL) AC CHARACTERISTICS DMA Symbol Parameter Min Max Units tACC DACK to WR or RD 0 ns tCAC RD or WR to DACK 0 ns tACD DACK to Data Valid 0 130 ns tCRQ RD or WR to DRQ Cleared 110 ns(1) NOTE 1 CL e 150 pF AC CHARACTERISTICS PORT 2 Symbol Parameter f(tCY)(3) Min Max Units tCP Port Control Setup Before Falling Edge of PROG 1 15 tCY b 28 55 ns(1) tPC Port Control Hold After Falling Edge of PROG 1 10 tCY 125 ns(2) tPR PROG to Time P2 Input Must Be Valid 8 15 tCY b 16 650 ns(1) tPF Input Data Hold Time 0 150 ns(2) tDP Output Data Setup Time 2 10 tCY 250 ns(1) tPD Output Data Hold Time 1 10 tCY b 80 45 ns(2) tPP PROG Pulse Width 6 10 tCY 750 ns NOTES 1 CL e 80 pF 2 CL e 20 pF 3 tCY e 1 25 ms 18 UPI-C42 UPI-L42 AC CHARACTERISTICS PROGRAMMING (UPI-C42 AND UPI-L42) TA e 25 C g 5 C VCC e 6 25V g 0 25V VDDL e a 5V g 0 25V VDDH e 12 75V g 0 25V (87C42 87L42 ONLY) Symbol Parameter Min Max Units tAW Address Setup Time to RESETu 4tCY tWA Address Hold Time after RESETu 4tCY tDW Data in Setup Time to PROGv 4tCY tWD Data in Hold Time after PROGu 4tCY tPW Initial Program Pulse Width 95 105 ms tTW Test 0 Setup Time for Program Mode 4tCY tWT Test 0 Hold Time after Program Mode 4tCY tDO Test 0 to Data Out Delay 4tCY tWW RESET Pulse Width to Latch Address 4tCY tr tf PROG Rise and Fall Times 05 100 ms tCY CPU Operation Cycle Time 25 3 75 ms tRE RESET Setup Time before EAu 4tCY tOPW Overprogram Pulse Width 2 85 78 75 ms(1) tDE EA High to VDD High 1tCY NOTES 1 This variation is a function of the iteration counter value X 2 If TEST 0 is high tDO can be triggered by RESETu AC TESTING INPUT OUTPUT WAVEFORM AC TESTING LOAD CIRCUIT INPUT OUTPUT 290414 – 16 290414 – 17 19 UPI-C42 UPI-L42 DRIVING FROM AN EXTERNAL SOURCE 290414 – 18 290414 – 19 NOTE Rise and Fall Times Should Not See XTAL1 Configuration Table Exceed 10 ns Resistors to VCC are Needed to Ensure VIH e 3 5V if TTL Circuitry is Used LC OSCILLATOR MODE CRYSTAL OSCILLATOR MODE L C NOMINAL 1 45 H 20 pF 5 2 MHz fe 2q0LC 120 H 20 pF 3 2 MHz C a 3Cpp C e 2 290414 – 21 Cpp j 5– 10 pF C1 5 pF (STRAY 5 pF) Pin-to-Pin Capacitance C2 (CRYSTAL a STRAY) 8 pF C3 20 – 30 pF INCLUDING STRAY Crystal Series Resistance Should 290414 – 20 Each C Should be Approximately 20 pF including Stray Capacitance be Less Than 30X at 12 5 MHz XTAL1 Configuration Table XTAL1 Connection 2) 10 KX Resistor 1) to Ground 3) Not Connected to Ground Not recommended for CHMOS Recommended configuration for Low power configuration designs Causes approximately designs which will use both recommended for CHMOS only 16 mA of additional current flow NMOS and CHMOS parts This designs to provide lowest through the XTAL1 pin on UPI- configuration limits the additional possible power consumption C42 and approximately 11 mA of current through the XTAL1 pin to This configuration will not work additional current through XTAL1 approximately 1 mA while with the NMOS device on the UPI-L42 maintaining compatibility with the NMOS device 20 UPI-C42 UPI-L42 WAVEFORMS READ OPERATION DATA BUS BUFFER REGISTER 290414 – 22 WRITE OPERATION DATA BUS BUFFER REGISTER 290414 – 23 CLOCK TIMING 290414 – 24 21 UPI-C42 UPI-L42 WAVEFORMS (Continued) COMBINATION PROGRAM VERIFY MODE 290414 – 25 NOTES 1 A0 must be held low (0V) during program verify modes 2 For VIH VIH1 VIL VIL1 VDDH and VDDL please consult the D C Characteristics Table 3 When programming the 87C42 a 0 1 mF capacitor is required across VDD and ground to suppress spurious voltage transients which can damage the device VERIFY MODE 290414 – 26 NOTES 1 PROG must float if EA is low 2 PROG must float or e 5V when EA is high 3 P10 – P17 e 5V or must float 4 P24 – P27 e 5V or must float 5 A0 must be held low during programming verify modes 22 UPI-C42 UPI-L42 WAVEFORMS (Continued) DMA 290414 – 27 PORT 2 290414 – 28 PORT TIMING DURING EXTERNAL ACCESS (EA) 290414 – 29 On the Rising Edge of SYNC and EA is Enabled Port Data is Valid and can be Strobed On the Trailing Edge of Sync the Program Counter Contents are Available 23 UPI-C42 UPI-L42 Table 4 UPI Instruction Set Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles ACCUMULATOR DATA MOVES ADD A Rr Add register to A 1 1 MOV A Rr Move register to A 1 1 ADD A Rr Add data memory 1 1 MOV A Rr Move data memory 1 1 to A to A ADD A data Add immediate to A 2 2 MOV A data Move immediate to A 2 2 ADDC A Rr Add register to A 1 1 MOV Rr A Move A to register 1 1 with carry MOV Rr A Move A to data 1 1 ADDC A Rr Add data memory 1 1 memory to A with carry MOV Rr data Move immediate to 2 2 ADDC A data Add immediate 2 2 register to A with carry MOV Rr Move immediate to 2 2 ANL A Rr AND register to A 1 1 data data memory ANL A Rr AND data memory 1 1 MOV A PSW Move PSW to A 1 1 to A MOV PSW A Move A to PSW 1 1 ANL A data AND immediate to A 2 2 XCH A Rr Exchange A and 1 1 ORL A Rr OR register to A 1 1 register ORL A Rr OR data memory 1 1 XCH A Rr Exchange A and 1 1 to A data memory ORL A data OR immediate to A 2 2 XCHD A Rr Exchange digit of A 1 1 XRL A Rr Exclusive OR regis- 1 1 and register ter to A MOVP A A Move to A from 1 2 XRL A Rr Exclusive OR data 1 1 current page memory to A MOVP3 A A Move to A from 1 2 XRL A data Exclusive OR imme- 2 2 page 3 diate to A TIMER COUNTER INC A Increment A 1 1 MOV A T Read Timer Counter 1 1 DEC A Decrement A 1 1 MOV T A Load Timer Counter 1 1 CLR A Clear A 1 1 STRT T Start Timer 1 1 CPL A Complement A 1 1 STRT CNT Start Counter 1 1 DA A Decimal Adjust A 1 1 STOP TCNT Stop Timer Counter 1 1 SWAP A Swap nibbles of A 1 1 EN TCNTI Enable Timer 1 1 RL A Rotate A left 1 1 Counter Interrupt RLC A Rotate A left through 1 1 DIS TCNTI Disable Timer 1 1 carry Counter Interrupt RR A Rotate A right 1 1 RRC A Rotate A right 1 1 CONTROL through carry EN A20 Enable A20 Logic 1 1 EN DMA Enable DMA Hand- 1 1 INPUT OUTPUT shake Lines IN A Pp Input port to A 1 2 EN I Enable IBF Interrupt 1 1 OUTL Pp A Output A to port 1 2 ANL Pp data AND immediate to 2 2 DIS I Diable IBF Inter- 1 1 port rupt ORL Pp data OR immediate to 2 2 EN FLAGS Enable Master 1 1 port Interrupts IN A DBB Input DBB to A 1 1 SEL PMB0 Select Program 1 1 clear IBF memory bank 0 OUT DBB A Output A to DBB 1 1 SEL PMB1 Select Program 1 1 set OBF memory bank 1 MOV STS A A4 – A7 to Bits 4–7 of 1 1 SEL RB0 Select register 1 1 Status bank 0 MOVD A Pp Input Expander 1 2 SEL RB1 Select register 1 1 port to A bank 1 MOVD Pp A Output A to 1 2 UPI-C42 UPI-L42 Only Expander port ANLD Pp A AND A to Expander 1 2 port ORLD Pp A OR A to Expander 1 2 port 24 UPI-C42 UPI-L42 Table 4 UPI Instruction Set (Continued) Mnemonic Description Bytes Cycles Mnemonic Description Bytes Cycles CONTROL (Continued) BRANCH SUSPEND Invoke Suspend Power- 1 2 JMP addr Jump unconditional 2 2 down mode JMPP A Jump indirect 1 2 NOP No Operation 1 1 DJNZ Rr addr Decrement register 2 2 REGISTERS and jump INC Rr Increment register 1 1 JC addr Jump on Carry e 1 2 2 INC Rr Increment data 1 1 JNC addr Jump on Carry e 0 2 2 memory JZ addr Jump on A Zero 2 2 DEC Rr Decrement register 1 1 JNZ addr Jump on A not Zero 2 2 JT0 addr Jump on T0 e 1 2 2 SUBROUTINE JNT0 addr Jump on T0 e 0 2 2 CALL addr Jump to subroutine 2 2 JT1 addr Jump on T1 e 1 2 2 RET Return 1 2 JNT1 addr Jump on T1 e 0 2 2 RETR Return and restore 1 2 JF0 addr Jump on F0 Flag e 1 2 2 status JF1 addr Jump on F1 Flag e 1 2 2 FLAGS JTF addr Jump on Timer Flag 2 2 CLR C Clear Carry 1 1 e 1 Clear Flag CPL C Complement Carry 1 1 JNIBF addr Jump on IBF Flag 2 2 CLR F0 Clear Flag 0 1 1 e0 CPL F0 Complement Flag 0 1 1 JOBF addr Jump on OBF Flag 2 2 CLR F1 Clear F1 Flag 1 1 e1 CPL F1 Complement F1 Flag 1 1 JBb addr Jump on Accumula- 2 2 for Bit UPI-C42 UPI-L42 Only REVISION SUMMARY The following has been changed since Revision -003 1 Delete all references to standby power down mode The following has been changed since Revision -002 1 Added information on keyboard controller prod- uct family 2 Added IHI specification for the UPI-L42 The following has been changed since Revision -001 1 Added UPI-L42 references and specification 25