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Source PDF: /mnt/main/jmc-storage/docs/Hardware/Intel/UPI-452 CHMOS programmable IO processor.pdf Like all conversions the text below should be fully readable as UTF-8 unicode text. --------------------------------------------------------------- UPI-452 CHMOS PROGRAMMABLE I O PROCESSOR 83C452 - 8K c 8 Mask Programmable Internal ROM 80C452 - External ROM EPROM Y 83C452 80C452 3 5 to 14 MHz Clock Y Two 16-Bit Timer Counters Rate Y Boolean Processor Y Software Compatible with the MCS-51 Y Bit Addressable RAM Family Y 8 Interrupt Sources Y 128-Byte Bi-Directional FIFO Slave Interface Y Programmable Full Duplex Serial Channel Y Two DMA Channels Y 64K Program Memory Space Y 256 c 8-Bit Internal RAM Y 64K Data Memory Space Y 34 Additional Special Function Registers Y 68-Pin PGA and PLCC (See Packaging Spec Order 231369) Y 40 Programmable I O Lines The Intel UPI-452 (Universal Peripheral Interface) is a 68 pin CHMOS Slave I O Processor with a sophisticated bi-directional FIFO buffer interface on the slave bus and a two channel DMA processor on-chip The UPI-452 is the newest member of Intel’s UPI family of products It is a general-purpose slave I O Processor that allows the designer to grow a customized interface solution The UPI-452 contains a complete 80C51 with twice the on-chip data and program memory The sophisticated slave FIFO module acts as a buffer between the UPI-452 internal CPU and the external host CPU To both the external host and the internal CPU the FIFO module looks like a bi-directional bottomless buffer that can both read and write data The FIFO manages the transfer of data independent of the UPI-452 core CPU and generates an interrupt or DMA request to either CPU host or internal as a FIFO service request The FIFO consists of two channels the Input FIFO and the Output FIFO The division of the FIFO module array 128 bytes between Input channel and Output channel is programmable by the user Each FIFO byte has an additional logical ninth bit to distinguish between a data byte and a Data Stream Command byte Additionally Immediate Commands allow direct interrupt driven bi-directional communication between the UPI-452 internal CPU and external host CPU bypassing the FIFO The on-chip DMA processor allows high speed data transfers from one writeable memory space to another As many as 64K bytes can be transferred in a single DMA operation Three distinct memory spaces may be used in DMA operations Internal Data Memory External Data Memory and the Special Function Registers (including the FIFO IN FIFO OUT and Serial Channel Special Functions Registers) Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1996 November 1994 Order Number 231428-006 UPI-452 231428 – 1 Figure 1 Architectural Block Diagram 2 UPI-452 231428 – 2 Figure 1 Architectural Block Diagram (Continued) 3 UPI-452 TABLE OF CONTENTS CONTENTS PAGE Introduction 1 Table of Contents 4 List of Tables and Figures 5 Pin Description 7 Architectural Overview 10 Introduction 10 FIFO Buffer Interface 10 FIFO Programmable Features 11 Immediate Commands 12 DMA 12 FIFO Slave Interface Functional Description 12 Overview 12 Input FIFO Channel 13 Output FIFO Channel 14 Immediate Commands 16 Host Slave Interface Special Function Registers 18 Slave Interface Special Function Registers 18 External Host Interface Special Function Registers 20 FIFO Module External Host Interface 22 Overview 22 Slave Interface Address Decoding 22 Interrupts to the Host 22 DMA Requests to the Host 24 FIFO Module Internal CPU Interface 24 Overview 24 Internal CPU Access to FIFO via Software Instructions 24 General Purpose DMA Channels 25 Overview 25 Architecture 25 DMA Special Function Registers 26 DMA Transfer Modes 27 External Memory DMA 29 Latency 29 DMA Interrupt Vectors 29 Interrupts When DMA is Active 30 DMA Arbitration 30 Interrupts 32 Overview 32 FIFO Module Interrupts to Internal CPU 32 Interrupt Enabling and Priority 33 FIFO External Host Interface FIFO DMA Freeze Mode 35 Overview 35 Initialization 35 Invoking FIFO DMA Freeze Mode During Normal Operation 36 FIFO Module Special Function Register Operation During FIFO DMA Freeze Mode 37 Internal CPU Read Write of the FIFO During FIFO DMA Freeze Mode 41 Memory Organization 41 Accessing External Memory 41 Miscellaneous Special Function Register Descriptions 43 4 UPI-452 LIST OF TABLES AND FIGURES Figures 1 Architectural Block Diagram 2 2 UPI 452 68-Pin PLCC Pinout Diagram 6 3 UPI-452 Conceptual Block Diagram 10 4 UPI-452 Functional Block Diagram 11 5 Input FIFO Channel Functional Block Diagram 13 6 Output FIFO Channel Functional Block Diagram 15 7a Handshake Mechanisms for Handling Immediate Command IN Flowchart 17 7b Handshake Mechanisms for Handling Immediate Command OUT Flowchart 17 8 DMA Transfer from External to External Memory 31 9 DMA Transfer from External to Internal Memory 31 10 DMA Transfer from Internal to External Memory 31 11 DMA Transfer Waveform Internal to Internal Memory 32 12 Disabling FIFO to Host Slave Interface Timing Diagram 36 Tables 1 Input FIFO Channel Registers 13 2 Output FIFO Channel Registers 15 3 UPI-452 Address Decoding 23 4 DMA Accessible Special Function Registers 26 5 DMA Mode Control - PCON SFR 29 6 Interrupt Priority 32 7 Interrupt Vector Addresses 32 8 Slave Bus Interface Status During FIFO DMA Freeze Mode 35 9 FIFO SFR’s Characteristics During FIFO DMA Freeze Mode 38 10 Threshold SFRs Range of Values and Number of Bytes to be Transferred 39 11a Internal Memory Addressing 41 11b 80C51 Special Function Registers 42 11c UPI-452 Additional Special Function Registers 42 12 Program Status Word (PSW) 44 13 PCON Special Function Register 44 5 UPI-452 P C Board View As Viewed from the Component Side of the P C Board (Underside of Socket) 231428 – 32 Figure 2 UPI 452 68-Pin PLCC Pinout Diagram 6 UPI-452 UPI MICROCONTROLLER FAMILY These UPI Microcontrollers are fully supported by Intel’s development tools (ICE ASM and PLM) The UPI-452 joins the current members of the UPI microcontroller family UPI’s are derivatives of the MCS TM family of microcontrollers Because of their Packaging on-chip system bus interface UPI’s are designed to be system bus ‘‘slaves’’ while their microcontroller The 80C452 83C452 is available in a 68-pin PLCC counterparts are intended as system bus ‘‘masters’’ package UPI Family MCS Family RAM ROM (Slave (Master Speed (Bytes) (Bytes) Configuration) Configuration) 80C452 80C51 12 MHz 256 83C452 80C51 12 MHz 256 8K 80C452-1 80C51 14 MHz 256 83C452-1 80C51 14 MHz 256 8K UPI-452 PIN DESCRIPTIONS Symbol Pin Type Name and Function VSS 9 43 I Circuit Ground VCC 60 I a 5V power supply during normal and idle mode operation It is also the standby power pin for power down mode XTAL1 38 I Input to the oscillator’s high gain amplifier A crystal or external source can be used XTAL2 39 O Output from the high gain amplifier Port 0 I O Port 0 is an 8-bit open drain bi-directional I O port Port 0 can sink (AD0–AD7) eight LS TTL inputs It is also the multiplexed low-order address and P0 0 8 data local expansion bus during accesses to external memory 1 10 2 11 3 12 4 13 5 14 6 15 P0 7 16 7 UPI-452 UPI-452 PIN DESCRIPTIONS (Continued) Symbol Pin Type Name and Function Port 1 I O Port 1 is an 8-bit quasi-bi-directional I O port Port 1 can sink four (A0–A7) LS TTL inputs The alternate functions can only be activated if the (HLD HLDA) corresponding bit latch in the port SFR contains a 1 Otherwise the P1 0 7 port pin is stuck at 0 Pins P1 5 and P1 6 are multiplexed with HLD and HLDA respectively whose functions are defined as below 1 6 Port Pin Alternate Function 2 5 P1 5 HLD Local bus hold 3 4 input output signal 4 3 P1 6 HLDA Local bus hold 5 2 acknowledge input 6 1 P1 7 68 Port 2 I O Port 2 is an 8-bit quasi-bi-directional I O port It also emits the high- (A8–A15) order 8 bits of address when accessing local expansion bus P2 0 29 external memory Port 2 can sink four LS TTL inputs 1 28 2 27 3 25 4 24 5 23 6 22 7 21 Port 3 I O Port 3 is an 8-bit quasi-bi-directional I O port It is also multiplexed P3 0 67 with the interrupt timer local serial channel RD and WR 1 66 functions that are used by various options The alternate functions 2 65 can only be activated if the corresponding bit latch in the port SFR 3 64 contains a 1 Otherwise the port pin is stuck at 0 Port 3 can sink 4 63 four LS TTL inputs The alternate functions assigned to the pins of 5 62 Port 3 are as follows 6 61 Port Pin Alternate Function P3 7 59 P3 0 RxD Serial input port P3 1 TxD Serial output port P3 2 INT0 Interrupt 0 Input P3 3 INT1 Interrupt 1 Input P3 4 T0 Input to counter 0 P3 5 T1 Input to counter 1 P3 6 WR The write control signal latches the data from Port 0 outputs into the External Data Memory on the local bus P3 7 RD The read control signal latches the data from Port 0 outputs on the local bus 8 UPI-452 UPI-452 PIN DESCRIPTIONS (Continued) Symbol Pin Type Name and Function Port 4 I O Port 4 is an 8-bit quasi-bi-directional I O port Port 4 can sink P4 0 30 source four TTL inputs 1 2 32 3 33 4 34 5 35 6 36 7 37 RST 20 I A high level on this pin for two machine cycles while the oscillator is running resets the device An internal pulldown resistor permits Power-on reset using only a capacitor connected to VCC This pin does not receive the power down voltage as is the case for HMOS MCS-51 family members This function has been transferred to the VCC pin ALE 18 O Provides Address Latch Enable output used for latching the address into external memory during normal operation ALE can sink source eight LS TTL inputs PSEN 19 O The Program Store Enable output is a control signal that enables the external Program Memory to the bus during normal fetch operation PSEN can sink source eight LS TTL inputs EA 17 I When held at TTL high level the UPI-452 executes instructions from the internal ROM when the PC is less than 8192 (8K 2000H) When held at a TTL low level the UPI-452 fetches all instructions from external Program Memory DB0 58 I O Host Bus Interface is an 8-bit bi-directional bus It is used to transfer DB1 57 data and commands between the UPI-452 and the host processor DB2 56 This bus can sink source eight LS TTL inputs DB3 55 DB4 54 DB5 53 DB6 52 DB7 51 CS 44 I This pin is the Chip Select of the UPI-452 A0 40 I These three address lines are used to interface with the host A1 41 system They define the UPI-452 operations The interface is A2 42 compatible with the Intel microprocessors and the MULTIBUS READ 46 I This pin is the read strobe from the host CPU Activating this pin causes the UPI-452 to place the contents of the Output FIFO (either a command or data) or the Host Status Control Special Function Register on the Slave Data Bus WRITE 47 I This pin is the write strobe from the host Activating this pin will cause the value on the Slave Data Bus to be written into the register specified by A0 – A2 DRQIN 49 O This pin requests an input transfer from the host system whenever INTRQIN the Input Channel requires data DRQOUT 48 O This output pin requests an output transfer whenever the Output INTRQOUT Channel requires service If the external host to UPI-452 DMA is enabled and a Data Stream Command is at the Output FIFO DRQOUT is deactivated and INTRQ is activated (see ‘GENERAL PURPOSE DMA CHANNELS’ section) 9 UPI-452 UPI-452 PIN DESCRIPTIONS (Continued) Symbol Pin Type Name and Function INTRQ 50 O This output pin is used to interrupt the host processor when an Immediate Command Out or an error condition is encountered It is also used to interrupt the host processor when the FIFO requests service if the DMA is disabled and INTRQIN and INTRQOUT are not used DACK 45 I This pin is the DMA acknowledge for the host bus interface Input and Output Channels When activated a write command will cause the data on the Slave Data Bus to be written as data to the Input Channel (to the Input FIFO) A read command will cause the Output Channel to output data (from the Output FIFO) on to the Slave Data Bus This pin should be driven high ( a 5V) in systems which do not have a DMA controller (see Address Decoding) VCC 26 I a 5V power supply during operation ARCHITECTURAL OVERVIEW scription of the UPI-452’s core CPU functional blocks including Timers Counters Introduction I O Ports The UPI-452 slave microcontroller incorporates an Interrupt timing and control (other than FIFO and 80C51 with double the program and data memory a DMA interrupts) slave interface which allows it to be connected di- Serial Channel rectly to the host system bus as a peripheral a FIFO buffer module a two channel DMA processor and a Local Expansion Bus fifth I O port (Figure 3) The UPI-452 retains all of Program Data Memory structure the 80C51 architecture and is fully compatible with Power-Saving Modes of Operation the MCS-51 instruction set CHMOS Features The Special Function Register (SFR) interface con- Instruction Set cept introduced in the MCS-51 family of microcon- trollers has been expanded in the UPI-452 To the Figure 3 contains a conceptual block diagram of the 20 Special Function Registers of the MCS-51 the UPI-452 Figure 4 provides a functional block dia- UPI-452 adds 34 more These additional Special gram Function Registers like those of the MCS-51 pro- vide access to the UPI-452 functional elements in- cluding the FIFO DMA and added interrupt capabili- FIFO Buffer Interface ties Several of the 80C51 core Special Function Registers have also been expanded to support add- A unique feature of the UPI-452 is the incorporation ed features of the UPI-452 of a 128 byte FIFO array at the host-slave interface The FIFO allows asynchronous bi-directional trans- This data sheet describes the unique features of the fers between the host CPU and the internal CPU UPI-452 Refer to the 80C51 data sheet for a de- 231428 – 7 Figure 3 UPI-452 Conceptual Block Diagram 10 UPI-452 231428 – 8 Figure 4 UPI-452 Functional Block Diagram The division of the 128 bytes between Input and nel Boundary Pointer (CBP) SFR This register con- Output channels is user programmable allowing tains the number of address locations assigned to maximum flexibility If the entire 128 byte FIFO is the Input channel The remaining address locations allocated to the Input channel a high performance are automatically assigned to the Output FIFO The Host can transfer up to 128 bytes at one time then CBP SFR can only be programmed by the internal dedicate its resources to other functions while the CPU during FIFO DMA Freeze Mode (See FIFO-Ex- internal CPU processes the data in the FIFO Vari- ternal Host Interface FIFO DMA Freeze Mode de- ous handshake signals allow the external Host to scription) The CBP is initialized to 40H (64 bytes) operate independently and without frequent monitor- upon reset ing of the UPI-452 internal CPU The FIFO Buffer insures that the slave processor receives data in the The number in the Channel Boundary Pointer SFR is same order that it was sent by the host without the actually the first address location of the Output need to keep track of addresses Three slave bus FIFO Writing to the CBP SFR reassigns the Input interface handshake methods are supported by the and Output FIFO address space Whenever the CBP UPI-452 DMA Interrupt and Polled is written the Input FIFO pointers are reset to zero and the Output FIFO pointers are set to the value in The FIFO is nine bits wide The ninth bit acts as a the CBP SFR command data flag Commands written to the FIFO All of the FIFO space may be assigned to one chan- by either the host or internal CPU are called Data nel In such a situation the other channel’s data path Stream Commands or DSCs DSCs are written to consists of a single SFR (FIFO IN COMMAND IN or the input FIFO by the Host via a unique external FIFO OUT COMMAND OUT SFR) location address DSCs are written to the output FIFO by the internal CPU via the COMMAND OUT Special Func- CBP Input FIFO Output FIFO tion Register (SFR) When encountered by the host Register Size Size or internal CPU a Data Stream Command can be 0 1 128 used as an address vector to user defined service 1 1 128 routines DSCs provide synchronization of data and 2 2 126 commands between the Host and internal CPU 3 3 125 4 4 124 FIFO PROGRAMMABLE FEATURES    7B 123 5 7C 124 4 Size of Input Output Channels 7D 125 3 7E 128 1 The 128 bytes of FIFO space can be allocated be- 7F 128 1 tween the Input and Output channels via the Chan- 11 UPI-452 FIFO Read Write Pointers DMA These normally operate in auto-increment (and auto- The UPI-452 contains a two channel internal DMA rollover) mode but can be reassigned by the internal controller which allows transfer of data between any CPU during FIFO DMA Freeze Mode (See FIFO-Ex- of the three writeable memory spaces Internal Data ternal Host Interface FIFO DMA Freeze Mode de- Memory External Load Expansion Bus Data Memo- scription) ry and the Special Function Register array The Spe- cial Function Register array appears as a set of unique dedicated memory addresses which may be Threshold Register used as either the source or destination address of a DMA transfer Each DMA channel is independently The Input FIFO Threshold SFR contains the number programmable via dedicated Special Function Reg- of empty bytes that must be available in the Input isters for mode source and destination addresses FIFO to generate a Host interrupt The Output FIFO and byte count to be transferred Each DMA channel Threshold SFR contains the number of bytes data has four programmable modes and or DSC(s) that must be in the FIFO before an interrupt is generated The Threshold feature pre- Alternate Cycle Mode vents the Host from being interrupted each time the Burst Mode FIFO needs to load or unload one byte of data The FIFO or Serial Channel Demand Mode thresholds therefore allow the FIFO’s operation to be adjusted to the speed of the Host optimizing the External Demand Mode overall interface performance A complete description of each mode and DMA op- NOTE eration may be found in the section titled ‘‘General DSC’s should be allowed to be written into the out- Purpose DMA Channels’’ put FIFO by the UPI-452 code only when the serv- ice request is law The service request can be mon- itored by b7 of OTHR This guideline will elimate FIFO SLAVE INTERFACE the possibility of a DSC being written to the output FUNCTIONAL DESCRIPTION FIFO with the intention of setting the service re- quest while having the number of bytes in the out- put FIFO below the threshold This condition can Overview occur if the FIFO contains at least two bytes the service request is being asserted and the host The FIFO is a 128 Byte RAM array with recirculating reads from the output FIFO until one byte remains pointers to manage the read and write accesses The FIFO consists of an Input and an Output chan- nel Access cycles to the FIFO by the internal CPU Immediate Commands and external Host are interleaved and appear to be occurring concurrently to both the internal CPU and The UPI-452 provides in addition to data and DSCs external Host Interleaving access cycles ensures a third direct means of communication between the efficient use of this shared resource The internal external Host and internal CPU called Immediate CPU accesses the FIFO in the same way it would Commands As the name implies an Immediate access any of the Special Function Registers e g Command is available to the receiving CPU immedi- direct and register indirect addressing as well as ar- ately via an interrupt without being entered into the ithmetric and logical instructions FIFO as are Data Stream Commands Like Data Stream Commands Immediate Commands are writ- ten either via a unique external address by the host CPU or via dedicated SFR by the internal CPU The DSC and or Immediate Command interface may be defined as either Interrupt or Polled under user program control via the Interrupt Enable (IE) Slave Control Register (SLCON) and Interrupt En- able Priority (IEP) Special Function Registers for the internal CPU and via the Host Control SFR for the external Host CPU 12 UPI-452 Input FIFO Channel The Input FIFO Channel provides for data transfer from the external Host to the internal CPU (Figure 5) The registers associated with the Input Channel during normal operation are listed in Table 1 Table 1 Input FIFO Channel Registers Register Name Description 1) Input Buffer Latch Host CPU Write only 2) FIFO IN SFR Internal CPU Read only 3) COMMAND IN SFR Internal CPU Read only 4) Input FIFO Read Pointer SFR Internal CPU Read only 5) Input FIFO Write Pointer SFR Internal CPU Read only 6) Input FIFO Threshold SFR Internal CPU Read only See ‘‘FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE’’ section for FIFO DMA Freeze Mode SFR characteristics description 231428 – 9 Figure 5 Input FIFO Channel Functional Block Diagram 13 UPI-452 The host CPU writes data and Data Stream Com- FIFO is full an external interrupt if enabled is sent mands into the Input Buffer Latch on the rising edge to the host to signal the overrun condition The of the external WR signal External addressing de- writes are ignored by the FIFO control logic Similar- termines whether the byte is a data byte or Data ly an internal CPU read of an empty FIFO will cause Stream Command and the FIFO logic sets the ninth an underrun error interrupt to be generated to the bit of the FIFO accordingly as the byte is moved internal CPU and a value of ‘‘0FFH’’ will be read by from the Input Buffer Latch into the FIFO A ‘‘1’’ in the internal CPU the ninth bit indicates that the incoming byte is a Data Stream Command The internal CPU reads The Read Pointer SFR holds the address of the next data bytes via the FIFO IN SFR and Data Stream byte to be read from the Input FIFO An Input FIFO Commands via the COMMAND IN SFR read operation post-increments the Input Read Pointer SFR and loads a new data byte into the A Data Stream Command will generate an interrupt FIFO IN SFR or a Data Stream Command into the to the internal CPU prior to being read and after COMMAND IN SFR at the end of the read cycle completion of the previous operation The DSC can then be read via the COMMAND IN SFR Data can An Input FIFO Request for Service (via DMA Inter- only be read via the FIFO IN SFR and Data Stream rupt or a flag) is generated to the Host whenever Commands via the COMMAND IN SFR Attempting more data can be written into the Input FIFO For to read Data Stream Commands as data by address- efficient utilization of the Host a ‘‘threshold’’ value ing the FIFO IN SFR will result in ‘‘0FFH’’ being can be programmed into the Input FIFO Threshold read and the Input FIFO Read Pointer will remain SFR The range of values of the Input FIFO Thresh- intact (This prevents accidental misreading of Data old SFR can be from 0 to (CBP-3) The Request for Stream Commands ) Attempting to read data as Service Interrupt is generated only after the Input Data Stream Commands will have the same conse- FIFO has room to accommodate a threshold number quence of bytes or more The threshold is equal to the total number of bytes assigned to the Input FIFO (CBP) The Input FIFO Channel addressing is controlled by minus the number of bytes programmed in the Input the Input FIFO Read and Write Pointer SFRs These FIFO Threshold SFR With this feature the Host is SFRs are read only registers during normal opera- assured that it can write at least a threshold number tion However during FIFO DMA Freeze Mode (See of bytes to the Input FIFO channel without worrying FIFO-External Host Interface FIFO DMA Freeze about an overrun condition Once the Request for Mode description) the internal CPU has write ac- Service is generated it remains active until the Input cess to them Any write to these registers in normal FIFO becomes full mode will have no effect The Input Write Pointer SFR contains the address location to which data commands are written from the Input Buffer Latch Output FIFO Channel The write pointer is automatically incremented after each write and is reset to zero if equal to the CBP The Output FIFO Channel provides data transfer as the Input FIFO operates as a circular buffer from the UPI-452 internal CPU to the external Host (Figure 6) If a write is performed on an empty FIFO the first byte is also written into the FIFO IN or COMMAND The registers associated with the Output Channel IN SFR If the Host continues writing while the Input during normal operation are listed in Table 2 14 UPI-452 231428 – 10 Figure 6 Output FIFO Channel Functional Block Diagram Table 2 Output FIFO Channel Registers Register Name Description 1) Output Buffer Latch Host CPU Read only 2) FIFO OUT SFR Internal CPU Read and Write 3) COMMAND OUT SFR Internal CPU Read and Write 4) Output FIFO Read Pointer SFR Internal CPU Read only 5) Output FIFO Write Pointer SFR Internal CPU Read only 6) Output FIFO Threshold SFR Internal CPU Read only See ‘‘FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE’’ section for FIFO DMA Freeze Mode register characteristics description 15 UPI-452 The UPI-452 internal CPU transfers data to the Out- 2 ) The second type of Request for Service is called put FIFO via the FIFO OUT SFR and commands via ‘‘Flush Mode’’ and occurs when the internal CPU the COMMAND OUT SFR If the byte is written to writes a Data Stream Command into the Output the COMMAND OUT SFR the ninth bit is automati- FIFO Its purpose is to ensure that a data block cally set ( e 1) to indicate a Data Stream Command entered into the Output FIFO which is less than If the byte is written to the FIFO OUT SFR the ninth the programmed threshold will generate a Re- bit is cleared ( e 0) Thus the FIFO OUT and COM- quest for Service interrupt if enabled and be MAND OUT SFRs are the same but the address de- read or ‘‘Flushed’’ from the Output FIFO by the termines whether the byte entered in the FIFO is a external host CPU regardless of the status of the DSC or data byte OTHR SFR The Output FIFO preloads a byte into the Output NOTE Buffer Latch When the Host issues a RD signal The host port read or write strobe (TPW) should be the data is immediately read from the Output Buffer limited to a maximum of 4 TCLCL This guideline Latch The next data byte is then loaded into the will eliminate a potential output FIFO Request lock- Output Buffer Latch a flag is set and an interrupt if up from occurring if the host reads the last byte enabled is generated if the byte is a DSC (ninth bit from the output FIFO while the UPI-452 is begin- is set) The operation is carefully timed such that an ning to write another byte to the output FIFO interrupt can be generated in time for it to be recog- nized by the Host before its next read instruction Internal CPU write and external Host read opera- Immediate Commands tions are interleaved at the FIFO so that they appear to be occurring concurrently Immediate Commands provide direct communica- tion between the external Host and UPI-452 Unlike The Output FIFO read and write pointer operation is Data Stream Commands which are entered into the the same as for the Input Channel Writing to the FIFO the Immediate Command is available to the FIFO OUT or COMMAND OUT SFRs will increment receiving CPU directly bypassing the FIFO The Im- the Output Write Pointer SFR but reading from it will mediate Command can serve as a program vector leave the write pointer unchanged A rollover of the pointing into a jump table in the recipients software Output FIFO Write Pointer causes the pointer to be Immediate Command Interrupts are generated if en- reset to the value in the Channel Boundary Pointer abled and a bit in the appropriate Status Register is (CBP) SFR set when an Immediate Command is input or output A similar bit is provided to acknowledge when an If the external host attempts to read a Data Stream Immediate Command has been read and whether Command as a data byte it will result in invalid data the register is available to receive another com- (0FFH) being read The DSC is not lost because the mand The bits are reset when the Immediate Com- invalid read does not increment the pointer Similarly mands are read Two Special Function Registers are attempting to read a data byte as a Data Stream dedicated to the Immediate Command interface Ex- Command has the same result ternal addressing determines whether the Host is accessing the Input FIFO or the Immediate Com- A Request for Service is generated to the external mand IN (IMIN) SFR The internal CPU writes Imme- Host under the following two conditions diate Commands to the Immediate Command OUT 1 ) Whenever the internal CPU has written a thresh- (IMOUT) SFR old number of bytes or more into the Output FIFO (threshold e (OTHR) a 1) The threshold num- Both processors have the ability to enable or disable Immediate Command Interrupts By disabling the in- ber should be chosen such that the bus latency terrupt the recipient of the Immediate Command time for the external Host does not result in a can poll the status SFR and read the Immediate FIFO overrun error condition on the internal CPU Command at its convenience Immediate Com- side The threshold limit should be large enough mands should only be written when the appropriate to make a bus request by the UPI-452 to the ex- Immediate Command SFR is empty (as indicated in ternal host CPU worthwhile Once a request for the appropriate status SFR HSTAT SSTAT) Simi- service is generated the request remains active larly the Immediate Command SFR should only be until the Output FIFO becomes empty The range read when there is data in the Register of values of the FIFO Output Threshold (OTHR) SFR is from 2 to (80H-CBP)-1 The threshold The flowcharts in Figure 7a and 7b illustrate the number can be programmed via the OTHR SFR proper handshake mechanisms between the exter- nal Host and internal CPU when handling Immediate Commands 16 UPI-452 231428 – 11 231428 – 12 Figure 7a Handshake Mechanisms for Handling Figure 7b Handshake Mechanisms for Handling Immediate Command IN Flowchart Immediate Command OUT Flowchart 17 UPI-452 HOST SLAVE INTERFACE SPECIAL FUNCTION REGISTERS Slave Interface Special Function Registers The Internal CPU interfaces with the FIFO slave module via the following registers 1) Mode Special Function Register (MODE) 2) Slave Control Special Function Register (SLCON) 3) Slave Status Special Function Register (SSTAT) Each register resides in the SFR Array and is accessible via all direct addressing modes except bit Only the Slave Control Register (SLCON) is bit addressable 1) MODE Special Function Register (MODE) The MODE SFR provides the primary control of the external host-FIFO interface It is included in the SFR Array so that the internal CPU can configure the external host-FIFO interface should the user decide that the UPI-452 slave initialize itself independent of the external host CPU The MODE SFR can be directly modified by the internal CPU through direct address instructions It can also be indirectly modified by the external host CPU by setting up a MODE SFR service routine in the UPI-452 program memory and having the host issue a Command either Immediate or DSC to vector to that routine Symbolic Physical Address Address MODE MD6 MD5 MD4 0F9H (MSB) (LSB) Status On Reset 1 0 0 0 1 1 1 1 MD7 (reserved) MD6 Request for Service to external CPU via 1 e DMA (DRQIN DRQOUT) request to external host when the Input or Output FIFO channel re- quests service 0 e Interrupt (INTRQIN INTRQOUT or INTRQ) to external host when the Input or Output FIFO channel requests service or a DSC is encountered in the I O Buffer Latch MD5 Configure DRQIN INTRQIN and DRQOUT INTRQOUT to be either 1 e Enable (Actively driven) 0 e Disable (Tri-state) MD4 Configure INTRQ to be either 1 e Enable (Actively driven) 0 e Disable (Tri-state) MD3 (reserved) MD2 (reserved) MD1 (reserved) MD0 (reserved) 2) Slave Control SFR (SLCON) The Slave Control SFR is used to configure the FIFO-internal CPU interface All interrupts are to the internal CPU 18 UPI-452 Symbolic Physical Address Address SLCON IFI OFI ICII ICOI FRZ IFRS OFRS 0E8H (MSB) (LSB) Status On Reset 0 0 0 0 0 1 0 0 IFI Enable Input FIFO Interrupt (due to Underrun Error Condition Data Stream Command or Request Service) 1 e Enable 0 e Disable OFI Enable Output FIFO Interrupt (due to Overrun Error Condition or Request Service) 1 e Enable 0 e Disable Note If the DMA is configured to service a FIFO demand then the Request for Service Interrupt is not generated ICII Generate Interrupt when a command is written to the Immediate Command in Register 1 e Enable 0 e Disable ICOI Generate Interrupt when Immediate Command Out Register is Available 1 e Enable 0 e Disable FRZ Enable FIFO DMA Freeze Mode 1 e Normal operation 0 e FIFO DMA Freeze Mode SC2 (reserved) IFRS Input FIFO Channel Request for Service 1 e Request when Input FIFO not empty 0 e Request when Input FIFO full OFRS Output FIFO Channel Request for Service 1 e Request when Output FIFO not full 0 e Channel Request when Output FIFO empty NOTES A ‘1’ will be read from all SFR reserved locations except HCON SFR HC0 and HC2 ‘reserved’ these locations are reserved for future use by Intel Corporation 3) Slave Status SFR (SSTAT) The bits in the Slave Status SFR reflect the status of the FIFO-internal CPU interface It can be read during an internal interrupt service routine to determine the nature of the interrupt or read during a polling sequence to determine a course of action Symbolic Physical Address Address SSTAT SST7 SST6 SST5 SST4 SST3 SST2 SST1 SST0 0E9H w Output FIFO Status x w Input FIFO Status x Status On Reset 1 0 0 0 1 1 1 1 (MSB) (LSB) 19 UPI-452 SST7 Output FIFO Overrun Error Condition 1 e No Error 0 e Error (latched until Slave Status SFR is read) SST6 Immediate Command Out Register Status 1 e Full (i e Host CPU has not read previous Immediate Command Out sent by internal CPU) 0 e Available SST5 FIFO DMA Freeze Mode Status 1 e Normal Operation 0 e FIFO DMA Freeze Mode in Progress SST4 Output FIFO Request for Service Flag 1 e Output FIFO does not request service 0 e Output FIFO requests service SST3 Input FIFO Underrun Error Condition Flag 1 e No Underrun Error 0 e Underrun Error (latched until Slave Status SFR is read) SST2 Immediate Command In SFR Status 1 e Empty 0 e Immediate Command received from host CPU SST1 Data Stream Command Data at Input FIFO Flag 1 e Data (not DSC) 0 e DSC (at COMMAND IN SFR) SST0 Input FIFO Request For Service Flag 1 e Input FIFO Does Not Request Service 0 e Input FIFO Request for Service EXTERNAL HOST INTERFACE SPECIAL FUNCTION REGISTERS The external host CPU has direct access to the following SFRs 1) Host Control Special Function Register 2) Host Status Special Function Register It can also access other SFRs by commanding the internal CPU to change them accordingly via Data Stream Commands or Immediate Commands The protocol for implementing this is entirely determined by the user 1) Host Control SFR (HCON) By writing to the Host Control SFR the host can enable or disable FIFO interrupts and DMA requests and can reset the UPI-452 Symbolic Physical Address Address HCON HC7 HC6 HC5 HC4 HC3 HC1 0E7H (MSB) (LSB) Status On Reset 0 0 0 0 0 0 0 0 20 UPI-452 HC7 Enable Output FIFO Interrupt due to Underrun Error Condition Data Stream Command or Service Request 1 e Enable 0 e Disable HC6 Enable Input FIFO Interrupt due to Overrun Error Condition or Service Request 1 e Enable 0 e Disable HC5 Enable the generation of the Interrupt due to Immediate Command Out being present 1 e Enable 0 e Disable HC4 Enable the Interrupt due to the Immediate Command In Register being Available for a new Immediate Command byte 1 e Enable 0 e Disable HC3 Reset UPI-452 1 e Software RESET 0 e Normal Operation HC2 (reserved) HC1 Select between INTRQ and INTRQIN INTRQOUT as Request for Service interrupt signal when DMA is disabled 1 e INTRQ 0 e INTRQIN or INTRQOUT HC0 (reserved) NOTES A ‘1’ will be read from all SFR reserved locations except HCON SFR HC0 and HC2 ‘reserved’ these locations are reserved for future use by Intel Corporation 2) Host Status SFR (HSTAT) The Host Status SFR provides information on the FIFO-Host Interface and can be used to determine the source of an external interrupt during polling Like the Slave Status SFR the Host Status SFR reflects the current status of the FIFO-external host interface Symbolic Physical Address Address HSTAT HST7 HST6 HST5 HST4 HST3 HST2 HST1 HST0 0E6H w Output FIFO Status x w Input FIFO Status x Status On Reset 1 1 1 1 1 1 0 1 1 (MSB) (LSB) 21 UPI-452 HST7 Output FIFO Underrun Error Condition FIFO MODULE - EXTERNAL HOST 1 e No Underrun Error 0 e Underrun Error (latched until Host INTERFACE Status Register is read) Overview HST6 Immediate Command Out SFR Status 1 e Empty The FIFO-external Host interface supports high speed asynchronous bi-directional 8-bit data trans- 0 e Immediate Command Present fers The host interface is fully compatible with Intel HST5 Data Stream Command Data at Output microprocessor local busses and with MULTIBUS FIFO Status The FIFO has two specialized DMA request pins for 1 e Data (not DSC) Input and Output FIFO channel DMA requests 0 e DSC (present at Output FIFO COM- These are multiplexed to provide a dedicated Re- MAND OUT SFR) quest for Service interrupt (DRQIN INTRQIN (Note Only if HST4 e 0 if HST4 e 1 then un- DRQOUT INTRQOUT) determined) The external Host can program under user defined HST4 Output FIFO Request for Service Status protocol thresholds into the FIFO Input and Output 1 e No Request for Service Threshold SFRs which determine when the FIFO 0 e Output FIFO Request for Service due to Request for Service interrupt is generated to the a Output FIFO containing the threshold Host CPU The FIFO module external Host interface number of bytes or more is configured by the internal CPU via the MODE b Internal CPU sending a block of data ter- SFR ‘‘The external Host can enable and disable minated by a DSC (DSC Flush Mode) Host interface interrupts via the Host Control SFR ’’ Data Stream Commands in the Input FIFO channel HST3 Input FIFO Overrun Error Condition allow the Host to influence the processing of data 1 e No Overrun Error blocks and are sent with the data flow to maintain 0 e Overrun Error (latched until Host Status synchronization Data Stream Commands in the Register is read) Output FIFO Channel allow the internal CPU to per- HST2 Immediate Command In SFR Status form the same function and also to set the Output 1 e Full (i e Internal CPU has not read pre- FIFO Request Service status logic to the host CPU vious Immediate Command sent by Host) regardless of the programmed value in the Thresh- 0 e Empty old SFR Reset value ‘1’ if read by the external Host Slave Interface Address Decoding ‘0’ if read by internal CPU (reads shadow The UPI-452 determines the desired Host function latch - see FIFO DMA Freeze Mode descrip- through address decoding The lower three bits of tion) the address as well as the READ WRITE Chip Se- HST1 FIFO DMA Freeze Mode Status lect (CS) and DMA Acknowledge (DACK) are used 1 e Freeze Mode in progress for decoding Table 3 shows the pin states and the (In Freeze Mode the bits of the Host Status Read or Write operations associated with each con- SFR are forced to a ‘1’ initially to prevent the figuration external Host from attempting to access the FIFO The definition of the Host Status SFR Interrupts to the Host bits during FIFO DMA Freeze Mode can be The UPI-452 interrupts the external Host via the found in FIFO DMA Freeze Mode descrip- INTRQ pin In addition the DRQIN and DRQOUT tion) pins can be multiplexed as interrupt request lines 0 e Normal Operation INTRQIN and INTRQOUT respectively when DMA HST0 Input FIFO Request Service Status is disabled This provides two special FIFO ‘‘Re- 1 e Input FIFO does not request service quest for Service’’ interrupts 0 e Input FIFO request service due to the Input FIFO containing enough space for the There are eight FIFO-related interrupt sources two host to write the threshold number of bytes from The Input FIFO three from The Output FIFO or more one from the Immediate Command Out SFR one from the Immediate Command IN SFR and one due to FIFO DMA Freeze Mode INPUT FIFO The Input FIFO interrupt is generated whenever a The Input FIFO contains space for a threshold number of bytes 22 UPI-452 Table 3 UPI-452 Address Decoding DACK CS A2 A1 A0 Read Write 1 1 X X X No Operation No Operation 1 0 0 0 0 Data or DMA from Output FIFO Channel Data or DMA to Input FIFO Channel 1 0 0 0 1 Data Stream Command from Output FIFO Channel Data Stream Command to Input FIFO Channel 1 0 0 1 0 Host Status SFR Read Reserved 1 0 0 1 1 Host Control SFR Read Host Control SFR Write 1 0 1 0 0 Immediate Command SFR Read Immediate Command to SFR Write 1 0 1 1 X Reserved Reserved 0 X X X X DMA Data from Output FIFO Channel DMA Data to Input FIFO Channel 1 0 1 0 1 Reserved Reserved NOTES 1 Attempting to read a DSC as a data byte will result in invalid data being read The read pointers are not incremented so that the DSC is not lost Attempting to read a data byte as a DSC has the same result 2 If DACK is active the UPI-452 will attempt a DMA operation when RD or WR becomes active regardless of the DMA enable bit (MD6) in the MODE SFR Care should be taken when using DACK For proper operation DACK must be driven high ( a 5V) when not using DMA b When an Input FIFO overrun error condition ex- b An Immediate Command IN interrupt is generat- ists The appropriate bits in the Host Status SFR ed if enabled to the Host when the internal CPU are set and the interrupt is generated only if en- has read a byte from the Immediate Command IN abled (IMIN) SFR The read operation clears the Host Status SFR Immediate Command IN Status bit OUTPUT FIFO The Output FIFO Request for Serv- (HSTAT HST2) indicating that the Immediate ice Interrupt operates in a similar manner as the In- Command IN SFR is empty The corresponding put FIFO interrupt Slave Status (SSTAT) SFR bit is also set to indi- a When the FIFO contains the threshold number of cate an empty status Setting the Slave Status bytes or more SFR bit generates a FIFO-Slave Interface inter- b Output FIFO error condition interrupts are gener- rupt if enabled to the internal CPU (See Figure ated when the Output FIFO is underrun 7a Immediate Command IN Flowchart ) c Data Stream Command present in the Output NOTE Buffer Latch Immediate Command IN and OUT interrupts are ac- tually specific Request For Service interrupts to the A Data Stream Command interrupt is used to halt Host normal processing using the command as a vector to a service routine When DMA is disabled the user FIFO DMA FREEZE MODE When the internal CPU may program (through HC1) INTRQ to include FIFO invokes FIFO DMA Freeze Mode for example at re- Request for Service Interrupts or use INTRQIN and set or to reconfigure the FIFO interface INTRQ is INTRQOUT as Request for Service Interrupts activated The INTRQ can only be deactivated by IMMEDIATE COMMAND INTERRUPTS the external Host reading the Host Status SFR (HST1 remains active until FIFO DMA Freeze Mode a An Immediate Command Out Interrupt is generat- is disabled by the internal CPU) ed if enabled to the Host and the corresponding Host Status SFR bit (HSTAT HST6) is cleared Once an interrupt is generated INTRQ will remain when the internal CPU writes to the Immediate high until no interrupt generating condition exists Command OUT (IMOUT) SFR When the Host For a FIFO underrun overrun error interrupt the in- reads the Immediate Command OUT (IMOUT) terrupt condition is deactivated by the external Host SFR the corresponding bit in the Host Status reading the Host Status SFR An interrupt is serv- (HSTAT) SFR is set This causes the Slave Status iced by reading the Host Status SFR to determine Immediate Command OUT Status bit (SSTAT the source of the interrupt and vectoring the appro- SST6) to be cleared indicating that the Immediate priate service routine Command OUT (IMOUT) SFR is empty If en- abled a FIFO-Slave Interface will also be gener- ated to the internal CPU (See Figure 7b Immedi- ate Command OUT Flowchart ) 23 UPI-452 DMA Requests to the Host nation via the DMA0 DMA1 Source Address or Des- tination Address Special Function Registers The The UPI-452 generates two DMA requests DRQIN FIFO module manages the transfer of data between and DRQOUT to facilitate data transfer between the the external host and FIFO SFRs Host and the Input and Output FIFO channels A DMA acknowledge DACK is used as a chip select and initiates a data transfer The external READ and Internal CPU Access to FIFO Via WRITE signals select the Input and Output FIFO re- Software Instructions spectively The CS and address lines can also be used as a DMA acknowledge for processors with The internal CPU has access to the Input and Out- onboard DMA controllers which do not generate a put FIFOs via the FIFO IN COMMAND IN and FIFO DACK signal OUT COMMAND OUT SFRs which reside in the Special Function Register Array At the end of every The internal CPU can configure the UPI-452 to re- instruction that involves a read of the FIFO IN COM- quest service from the external host via DMA or in- MAND IN SFR the SFR is written over by a new terrupts by programming Mode SFR MD6 bit In ad- byte from the Input FIFO channel when available At dition the external Host enables DMA requests the end of every instruction that involves a write to through bits 6 and 7 of the Host Control SFR When the FIFO OUT COMMAND OUT SFR the new byte a DMA request is invoked the number of bytes trans- is written into the Output FIFO channel and the write ferred to the Input FIFO is the total number of bytes pointer is incremented after the write operation (post in the Input FIFO (as determined by the CBP SFR) incremented) minus the value programmed in the Input FIFO Threshold SFR The DMA request line is activated The internal CPU reads the Input FIFO by using the only when the Input FIFO has a threshold number of FIFO IN COMMAND IN SFR as the source register bytes that can be transferred in an instruction Those instructions which read the Input FIFO are listed below The Output FIFO DMA request is activated when a DSC is written by the internal CPU at the end of a ADD A FIFO IN COMMAND IN less than threshold size block of data (Flush Mode) ADDC A FIFO IN COMMAND IN or when the Output FIFO threshold is reached The PUSH FIFO IN COMMAND IN request remains active until the Input FIFO becomes ANL A FIFO IN COMMAND IN full or the Output FIFO becomes empty If a DSC is encountered during an Output FIFO DMA transfer ORL A FIFO IN COMMAND IN the DMA request is dropped until the DSC is read XRL A FIFO IN COMMAND IN The DMA request will be reactivated after the DSC is CJNE A FIFO IN COMMAND IN rel read and remains active until the Output FIFO be- SUBB A FIFO IN COMMAND IN comes empty or another DSC is encountered MOV direct FIFO IN COMMAND IN MOV Ri FIFO IN COMMAND IN FIFO MODULE - INTERNAL CPU MOV Rn FIFO IN COMMAND IN INTERFACE MOV A FIFO IN COMMAND IN After each access to these registers they are over- Overview written by a new byte from the FIFO The Input and Output FIFOs are accessed by the NOTE internal CPU through direct addressing of the FIFO Instructions which use the FIFO IN or COMMAND IN COMMAND IN and FIFO OUT COMMAND OUT IN SFR as both a source and destination register Special Function Registers All of the 80C51 instruc- will have the data destroyed as the next data byte tions involving direct addressing may be used to ac- is rewritten into the FIFO IN register at the end of cess the FIFO’s SFRs The FIFO IN COMMAND IN the instruction These instructions are not support- and Immediate Command In SFRs are actually read ed by the UPI-452 FIFO Data can only be read only registers and their Output counterparts are through the FIFO IN SFR and DSCs through the write only Internal DMA transfers data between In- COMMAND IN SFR Data read through the COM- ternal memory External Memory and the Special MAND IN SFR will be read as 0FFH and DSCs Function Registers The Special Function Registers read through the FIFO IN SFR will be read as appear as another group of dedicated memory ad- OFFH The Immediate Command in SFR is read dresses and are programmed as the source or desti- with the same instructions as the FIFO IN and COMMAND IN SFRs 24 UPI-452 The FIFO IN COMMAND IN and Immediate Com- dress Register (DAR) (Note Since the FIFO IN SFR mand In SFRs are read only registers Any write op- is a read only register the DMA transfer will be ig- eration performed on these registers will be ignored nored if it is used as a DMA DAR This is also true if and the FIFO pointers will remain intact the FIFO OUT SFR is used as a DMA SAR ) The internal CPU uses the FIFO OUT SFR to write Each DMA channel is software programmable to op- to the Output FIFO and any instruction which uses erate in either Block Mode or Demand Mode In the the FIFO OUT or COMMAND OUT SFR as a desti- Block Mode DMA transfers can be further pro- nation will invoke a FIFO write DSCs are differenti- grammed to take place in Burst Mode or Alternate ated from data by writing to the COMMAND OUT Cycle mode In Burst Mode the processor halts its SFR In the FIFO Data Stream Commands have the execution and dedicates its resources to the DMA ninth bit associated with the command byte set to transfer In Alternate Cycle Mode DMA cycles and ‘‘1’’ The instructions used to write to the Output instruction cycles occur alternately FIFO are listed below In Demand Mode a DMA transfer occurs only when MOV FIFO OUT COMMOUT A it is demanded Demands can be accepted from an MOV FIFO OUT COMMOUT direct external device (through External Interrupt pins MOV FIFO OUT COMMOUT Rn EXT0 EXT1) or from either the Serial Channel or POP FIFO OUT COMMOUT FIFO flags In this way a DMA transfer can be syn- chronized to an external device the FIFO or the Se- MOV FIFO OUT COMMOUT data rial Port If the External Interrupt is configured in MOV FIFO OUT COMMOUNT Ri Edge Mode a single byte transfer occurs per tran- sition The external interrupt itself will occur if en- NOTE abled If the External Interrupt is configured in Level Instructions which use the FIFO OUT COMMAND Mode DMA transfers continue until the External In- OUT SFRs as both a source and destination regis- terrupt request goes inactive or the byte count be- ter cause invalid data to be written into the Output comes zero The following flags activate Demand FIFO These instructions are not supported by the Mode transfers of one byte to from the FIFO or Seri- UPI-452 FIFO al Channel RI - Serial Channel Receiver Buffer Full GENERAL PURPOSE DMA CHANNELS TI - Serial Channel Transmitter Buffer Empty Overview Architecture There are two identical General Purpose DMA Chan- There are three 16 bit and one 8 bit Special Function nels on the UPI-452 which allow high speed data Registers associated with each DMA channel transfer from one writeable memory space to anoth-  The 16 bit Source Address SFR (SAR) points to er As many as 64K bytes can be transferred in a the source byte single DMA operation The following memory spaces can be used with DMA channels  The 16 bit Destination Address SFR (DAR) points to the destination  Internal Data Memory  The 16 bit Byte Count SFR (BCR) contains the  External Data Memory number of bytes to be transferred and is decre-  Special Function Registers mented when a byte transfer is accomplished  The DMA Control SFR (DCON) is eight bits wide The Special Function Register array appears as a and specifies the source memory space destina- limited group of dedicated memory addresses The tion memory space and the mode of operation Special Function Registers may be used in DMA transfer operations by specifying the SFR as the In Auto Increment mode the Source Address and source or destination address The Special Function or Destination Address is incremented when a byte Registers which may be used in DMA transfers are is transferred When a DMA transfer is complete listed in Table 4 Table 4 also shows whether the (BCR e 0) the DONE bit is set and a maskable SFR may be used as Source or Destination only or interrupt is generated The GO bit must be set to both start any DMA transfer (also the Slave Control SFR FRZ bit must be set to disable FIFO DMA Freeze The FIFO can be accessed during DMA by using the Mode) The two DMA channels are designated as FIFO IN SFR as the DMA Source Address Register DMA0 and DMA1 and their corresponding registers (SAR) or the FIFO OUT SFR as the Destination Ad- are suffixed by 0 or 1 e g SAR0 DAR1 etc 25 UPI-452 Table 4 DMA Accessible Special Function Registers Source Destination SFR Symbol Address Either Only Only Accumulator A ACC 0E0H Y B Register B 0F0H Y FIFO IN FIN 0EEH Y COMMAND IN CIN 0EFH Y FIFO OUT FOUT 0FEH Y COMMAND OUT COUT 0FFH Y Serial Data Buffer SBUF 099H Y Port 0 P0 080H Y Port 1 P1 090H Y Port 2 P2 0A0H Y Port 3 P3 0B0H Y Port 4 P4 0C0H Y DMA Special Function Registers DMA Control SFR DCON0 DCON1 Symbolic Physical Address Address DCON0 DAS IDA SAS ISA DM TM DONE GO 092H DCON1 DAS IDA SAS ISA DM TM DONE GO 093H (MSB) (LSB) Reset Status DCON0 and DCON1 e 00H Bit Definition DAS IDA Destination Address Space 0 0 External Data Memory without Auto-Increment 0 1 External Data Memory with Auto-Increment 1 0 Special Function Register 1 1 Internal Data Memory SAS ISA Source Address Space 0 0 External Data Memory without Auto-Increment 0 1 External Data Memory with Auto-Increment 1 0 Special Function Register 1 1 Internal Data Memory DM TM DMA Transfer Mode 0 0 Alternate-Cycle Transfer Mode 0 1 Burst Transfer Mode 1 0 FIFO or Serial Channel Demand Mode 1 1 External Demand Mode 26 UPI-452 DONE DMA transfer Flag service request is generated DMA transfer cycles are alternated with instruction execution cycles 0 DMA transfer is not completed DMA transfers are terminated as in FIFO Demand 1 DMA transfer is complete Mode NOTE This flag is set when contents of the Byte Count Output Channel SFR decrements to zero It is reset automatically The DMA is configured as in FIFO Demand Mode when the DMA vectors to its interrupt routine and transfers are initiated whenever an Output FIFO GO Enable DMA Transfer requests service DMA transfer cycles are alternated with instruction execution cycles DMA transfers are 0 Disable DMA transfer (in all modes) terminated as in FIFO Demand Mode 1 Enable DMA transfer If the DMA is in the Block mode start DMA transfer if The FIFO logic resets the interrupt flag after trans- possible If it is in the Demand mode ferring the byte so the interrupt is never generated enable the channel and wait for a de- mand Once the DMA is programmed to service the FIFO the request for service interrupt for the FIFO is inhib- NOTE ited until the DMA is done (BCR e 0) The GO bit is reset when the BCR decrements to zero 2 BURST MODE In BURST mode the DMA is initiated by setting the DMA Transfer Modes GO bit in the DCON SFR The DMA operation con- The following four modes of DMA operation are pos- tinues until BCR decrements to zero (zero byte sible in the UPI-452 count) then an interrupt is generated (if enabled) No interrupts are recognized during this DMA opera- tion once it has started 1 ALTERNATE-CYCLE MODE General Input Channel Alternate cycle mode is useful when CPU process- The FIFO Input Channel can be used in burst mode ing must occur during the DMA transfers In this by specifying the FIFO IN SFR as the DMA Source mode a DMA cycle and an instruction cycle occur Address DMA transfers begin when the GO bit in alternately The interrupt request is generated (if en- the DMA Control SFR is set The number of bytes to abled) at the end of the process i e when BCR dec- be transferred must be specified in the Byte Count rements to zero The transfer is initiated by setting SFR (BCR) and auto-incrementing of the SAR must the GO bit in the DCON SFR be disabled Once the GO bit is set nothing can in- terrupt the transfer of data until the BCR is zero In Alternate-Cycle FIFO Demand Mode this mode a Data Stream Command encountered in the FIFO will be held in the COMMAND IN SFR with Alternate cycle demand mode is useful for FIFO the pointers frozen and invalid data (FFH) will be transfers of a less urgent nature As mentioned be- read through the FIFO IN SFR If the input FIFO fore CPU instruction cycles are interleaved with becomes empty during the block transfer an 0FFH DMA transfer cycles allowing true parallel process- will be read until BCR decrements to zero ing This mode differs from FIFO Demand Mode in that Output Channel CPU instruction cycles must be interleaved with DMA transfers even if the FIFO is demanding DMA The Output FIFO Channel can be used in burst In FIFO Demand Mode CPU cycles would never oc- mode by specifying the FIFO OUT or COMMAND cur if the FIFO demand was present OUT SFR as the DMA Destination Address DMA transfers begin when the GO bit is set This mode can be used to send a block of data or a block of Input Channel Data Stream Commands If the FIFO becomes full The DMA is configured as in FIFO Demand Mode during the block transfer the remaining data will be and transfers are initiated whenever an Input FIFO lost 27 UPI-452 NOTE is not full or empty DMA transfers begin when the All interrupts including FIFO interrupts are not rec- Request For Service Flag is activated by the FIFO ognized in Burst Mode Burst Mode transfers logic and continue as long as the flag is active The should be used to service the FIFO only when the Flag remains active until one of the following occurs user is certain that no Data Stream Commands are 1) The FIFO becomes full in the block to be transferred (Input FIFO) and that the FIFO contains enough space to store the block 2) BCR e 0 (this generates a DMA interrupt and to be transferred In all other cases Alternate Cycle sets the DONE bit) or Demand Mode should be used As in Alternate Cycle FIFO Demand Mode the FIFO logic resets the interrupt flag after transferring the 3 FIFO AND SERIAL CHANNEL DEMAND byte so the interrupt is never generated MODES After the GO bit is set the DMA is activated if one of NOTES the following conditions takes place 1 If the output FIFO is configured as a one byte SAR(0 1) e FIFO IN and HIFRS flag is set buffer and the user program consists of two-cycle DAR(0 1) e FIFO OUT and HOFRS flag is set instructions only then Alternate-Cycle Mode should be used The HIFRS and HOFRS signals are internal flags 2 In non-auto increment mode for internal to exter- which are not accessible by software These flags nal or external to internal transfers the lower 8 bits are similar to the SST0 and SST4 flags in the Slave of the external address should not correspond to Status Register except that they are of the opposite the FIFO or Serial Port address polarity and once set they are not cleared until the Input FIFO becomes empty (HIFRS) or the Output FIFO Demand Mode FIFO becomes full (HOFRS) Although any DMA mode is possible using the FIFO buffer only FIFO Demand and Alternate Cycle FIFO Serial Channel Demand Mode Demand Modes are recommended FIFO Demand Mode DMA transfers using the input FIFO Channel Serial Channel Demand Mode is the logical choice are set-up by setting the GO bit and specifying the when using the Serial Port The DMAs can be acti- FIFO IN register as the DMA Source Address Regis- vated by one of the Serial Channel Flags Receiver ter The BCR should be set to the maximum number interrupt (RI) or Transmitter Interrupt (TI) of expected transfers The user must also program bit 1 of the Slave Control Register (SC1) to deter- SAR(0 1) e SBUF and RI flag is set mine whether the Slave Status (SSTAT) SFR FIFO DAR(0 1) e SBUF and TI flag is set Request For Service Flag will be activated when the FIFO becomes not empty or full Once the Request NOTE For Service Flag is activated by the FIFO the DMA TI flag must be set by software to initiate the first transfer begins and continues until the request flag transfer is deactivated While the request is active nothing can interrupt the DMA (i e it behaves like burst When the DMA transfer begins only one byte is mode) The DMA Request is held active until one of transferred at a time The serial port hardware auto- the following occurs matically resets the flag after completion of the transfer so an interrupt will not be generated unless 1) The FIFO becomes empty DMA servicing is held off due to the DMA being 2) A Data Stream Command is encountered (this done (BCR e 0) or when the Hold Hold Acknowl- generates a FIFO interrupt and DMA operation edge logic is used and the DMA does not own the resumes after the Data Stream Command is bus In this case a Serial Port interrupt may be gen- read) erated if enabled because of the status of the RI or 3) BCR e 0 (this generates a DMA interrupt and TI flags sets the DONE bit) In FIFO demand mode Alternate cycle FIFO de- DMA transfers to the Output FIFO Channel are simi- mand mode or Serial Port demand mode only one of lar The FIFO OUT or COMMAND OUT SFR is the the following registers (SBUF FIN or FOUT) should DMA Destination Address SFR and a transfer is be used as either the SAR or DAR registers to pre- started by setting the GO bit The user programs bit vent undesired transfers For example if SAR0 e 0 of the Slave Control SFR (SC0) to determine FIN and DAR0 e SBUF in demand mode the DMA whether a demand occurs when the Output FIFO transfer will start if either the HIFRS or TI flags are set 28 UPI-452 4 EXTERNAL DEMAND MODE ARBITER MODE In this mode the UPI-452 is the bus master It configures port pin P1 5 as HLD input The DMA can be initiated by an external device via and pin P1 6 as HLDA output When a device as- External interrupt 0 and 1 (INT0 INT1) pins The serts the HLD signal to use the local bus the UPI- INT0 pin demands DMA0 (Channel 0) and INT1 de- 452 asserts the HLDA signal after current instruction mands DMA1 (Channel 1) If the interrupts are con- execution is complete If the UPI-452 needs an ex- figured in edge mode a single byte transfer is ac- ternal access via a DMA channel it waits until the complished for every request Interrupts also result requester releases the bus HLD goes inactive (INT0 and INT1) after every byte transfer (if en- abled) If the interrupts are configured in level mode DISABLE MODE When external program memory is the DMA transfer continues until the request goes accessed by an instruction or by program counter inactive or BCR e 0 In either case a DMA interrupt overflow beyond the internal ROM address or exter- is generated (if enabled) when BCR e 0 The GO bit nal data memory is accessed by MOVX instructions must be set for the transfer to begin it is a local memory access and the HLD HLDA logic is not initiated When a DMA channel attempts data transfer to from the external data memory the EXTERNAL MEMORY DMA HLD HLDA logic is initiated as described below DMA transfers from the internal memory space to When transferring data to or from external memory the internal memory space does not initiate the via DMA the HOLD (HLD) and HOLD-ACKNOWL- HLD HLDA logic EDGE (HLDA) signals are used for handshaking The HOLD and HOLD-ACKNOWLEDGE are active The balance of the PCON SFR bits are described in low signals which arbitrate control of the local bus the ‘‘80C51 Register Description Power Control The UPI-452 can be used in a system where multi- SFR’’ section below masters are connected to a single parallel Address Data bus The HLD HLDA signals are used to share resources (memory peripherals etc ) among all the Latency processors on the local bus The UPI-452 can be configured in any of three different External Memory When the GO bit is set the UPI-452 finishes the Modes controlled by bits 5 and 6 (REQ ARB) in current instruction before starting the DMA opera- the PCON SFR (Table 5) Each mode is described tion Thus the maximum latency is 3 5 microseconds below (at 14 MHz) REQUESTER MODE In this mode the UPI-452 is not the bus master but must request the bus from DMA Interrupt Vectors another device The UPI-452 configures port pin Each DMA channel has a unique vectored interrupt P1 5 as a HLD output and pin P1 6 as a HLDA input associated with it There are two vectored interrupts The UPI-452 issues a HLD signal when it needs ex- associated with the two DMA channels The DMA ternal access for a DMA channel It uses the local interrupts are enabled and priorities set via the Inter- bus after receiving the HLDA signal from the bus rupt Enable and Priority SFR (see ‘‘Interrupts’’ sec- master and will not release the bus until its DMA tion) The interrupt priority scheme is similar to the operation is complete scheme in 80C51 Table 5 DMA MODE CONTROL - PCON SFR Symbolic Physical Address Address PCON ARB REQ 87H (MSB) (LSB) Defined as per MLS-51 Data Sheet Reset Status 00H Definition ARB REQ 0 0 HLD HLDA logic is disabled 0 1 The UPI-452 is in the Requester Mode 1 0 The UPI-452 is in the Arbiter Mode 1 1 Invalid 29 UPI-452 When a DMA operation is complete (BCR decre- If the UPI-452 (as a Requester) asserts a HLD signal ments to zero) the DONE flag in the respective to request a DMA transfer (see ‘‘External Memory DCON (DCON0 or DCON1) SFR is set If the DMA DMA’’)and its other DMA Channel requests a trans- interrupt is enabled the DONE flag is reset automat- fer before the HLDA signal is received the channel ically upon vectoring to the interrupt routine having higher priority is activated first A Burst Mode transfer on channel 0 can not be interrupted since DMA0 has the highest priority A Demand Mode Interrupts When DMA is Active transfer on channel 0 is the only type of activity that can interrupt a block transfer on DMA1 If a Burst Mode DMA transfer is in progress the in- terrupts are not serviced until the DMA transfer is If while executing a DMA transfer the Arbiter re- complete This is also true for level activated Exter- ceives a HLD signal and then before it can acknowl- nal Demand DMA transfers During Alternate Cycle edge its other DMA Channel requests a transfer it DMA transfers however the interrupts are serviced then completes the second DMA transfer before at the end of the DMA cycle After that DMA cycles sending the HLDA signal to release the bus to the and instruction execution cycles occur alternately In HLD request the case of edge activated External Demand Mode DMA transfers the interrupt is serviced at the end of DMA transfers may be held off under the following DMA transfer of that single byte conditions 1 A write to any of the DMA registers inhibits the DMA for one instruction cycle DMA Arbitration NOTE Only one of the two DMA channels is active at a An instruction cycle may be executed in 1 2 or 4 time except when both are configured in the Alter- machine cycles dependent on the instruction being nate Cycle mode In this case the DMA cycles and executed DMA transfers are only executed after Instruction Execution cycles occur in the following the completion of an instruction cycle never be- order tween machine cycles of a single instruction cycle 1 DMA Cycle 0 Similarly instruction cycles are only executed upon 2 Instruction execution completion of a DMA transfer whether it be a one machine cycle transfer or two machine cycles (for 3 DMA Cycle 1 ext to ext memory transfers) 4 Instruction execution 2 A single machine cycle DMA register read opera- tion (i e MOV A DCON0) will inhibit the DMA for DMA0 has priority over DMA1 during simultaneous one instruction cycle However a two cycle DMA activation of the two DMA channels If one DMA register read operation will not inhibit the DMA channel is active the other DMA channel if activat- (i e MOV P1 DCON0) ed waits until the first one is complete If the HOLD HOLD Acknowledge logic is enabled in If DMA0 is already in the Alternate Cycle mode and requestor mode the hold request will go active once DMA1 is activated in Alternate Cycle Mode it will the go bit has been set (for burst mode) and once take two instruction cycles before DMA1 is activated the demand flag is set (for demand mode) regard- (due to the priority of DMA0) Once DMA1 becomes less of whether the DMA is held off by one of the active the execution will follow the normal se- above conditions quence The DMA Transfer waveforms are in Figures 8-11 If DMA0 is already in the Alternate Cycle mode and DMA1 is activated in Burst Mode the DMA1 Burst transfer will follow the DMA0 Alternate Cycle trans- fer (after the completion of the next instruction) 30 UPI-452 231428 – 13 Figure 8 DMA Transfer from External Memory to External Memory 231428 – 14 Figure 9 DMA Transfer from External Memory to Internal Memory 231428 – 15 Figure 10 DMA Transfer from Internal Memory to External Memory 31 UPI-452 231428 – 16 Figure 11 DMA Transfer from Internal Memory to Internal Memory INTERNAL INTERRUPTS Table 6 Interrupt Priority Interrupt Source Priority Level (highest) Overview External Interrupt 0 0 The UPI-452 provides a total of eight interrupt sourc- Internal Timer Counter 0 1 es (Table 6) Their operation is the same as in the DMA Channel 0 Request 2 80C51 with the addition of three new interrupt External Interrupt 1 3 sources for the UPI-452 FIFO and DMA features DMA Channel 1 Request 4 These added interrupts have their enable and priori- Internal Timer Counter 1 5 ty bits in the Interrupt Enable and Priority (IEP) SFR FIFO - Slave Bus Interface 6 The IEP SFR is in addition to the 80C51 Interrupt Serial Channel 7 Enable (IE) and Interrupt Priority (IP) SFRs The add- (lowest) ed interrupt sources are also globally enabled or dis- abled by the EA bit in the Interrupt Enable SFR Ta- Table 7 Interrupt Vector Addresses ble 6 lists the eight interrupt sources in order of pri- Interrupt Source Starting Address ority Table 7 lists the eight interrupt sources and External Interrupt 0 3 (003H) their respective address vector location in program Internal Timer Counter 0 11 (00BH) memory (DMA interrupts are discussed in the ‘‘Gen- External Interrupt 1 19 (013H) eral Purpose DMA Channels’’ section Additional in- Internal Timer Counter 1 27 (01BH) terrupt information for Timer Counter Serial Chan- Serial Channel 35 (023H) nel External Interrupt may be found in the Microcon- troller Handbook for the 80C51 ) FIFO - Slave Bus Interface 43 (02BH) DMA Channel 0 Request 51 (033H) DMA Channel 1 Request 59 (03BH) FIFO Module Interrupts to Internal CPU The FIFO module generates interrupts to the inter- FIFO requests service when it becomes empty or nal CPU whenever the FIFO requests service or not full as determined by bit 0 of the Slave Control when a Data Stream Command is in the COMMAND SFR (OFRS) Request for Service interrupts are IN SFR The Input FIFO will request service whenev- generated only if enabled by the internal CPU via the er it becomes full or not empty depending on bit 1 of Interrupt Enable SFR and the Slave Control Regis- the Slave Control SFR (IFRS) Similarly the Output ter 32 UPI-452 A Data Stream Command Interrupt is generated Immediate Command OUT bit (SSTAT SST6) to whenever there is a Data Stream Command in the be set and the corresponding Host Status bit COMMAND IN SFR The interrupt is generated to (HSTAT HST6) to be cleared indicating the SFR is ensure that the internal interrupt is recognized be- empty When the internal CPU writes to the Imme- fore another instruction is executed diate Command OUT SFR the Host Status bit is set and Slave Status bit is cleared to indicate the SFR is full (See Figure 7b Immediate Command Immediate Command Interrupts OUT Flowchart ) a An Immediate Command IN interrupt is generat- ed if enabled to the internal CPU when the Host NOTE has written to the Immediate Command IN (IMIN) Immediate Command IN and OUT interrupts are ac- SFR The write operation clears the Slave Status tually specific FIFO-Slave Interface interrupts to the SFR bit (SSTAT SST2) and sets the Host Status internal CPU SFR bit (HSTAT HST2) to indicate that a byte is present in the Immediate Command IN SFR One instruction from the main program is executed When the internal CPU reads the Immediate Com- between two consecutive interrupt service routines mand IN (IMIN) SFR the Slave Status SFR status as in the 80C51 However if the second interrupt bit is set and the Host Status SFR status bit is service routine is due to a Data Stream Command cleared indicating the IMIN SFR is empty Clear- Interrupt the main program instruction is not execut- ing the Host Status SFR bit will cause a Request ed (to prevent misreading of invalid data) For Service (INTRQ) interrupt if enabled to signal the Host that the IMIN SFR is empty (See Figure 7a Immediate Command IN Flowchart ) Interrupt Enabling and Priority b An Immediate Command OUT interrupt is gener- Each of the three interrupt special function registers ated if enabled to the internal CPU when the (IE IP and IEP) is listed below with its corresponding Host has read the Immediate Command OUT bit definitions SFR The Host read causes the Slave Status Interrupt Enable SFR (IE) Symbolic Physical Address Address IE EA ES ET1 EX1 ET0 EX0 0A8H (MSB) (LSB) Symbol Position Function EA IE 7 Enables all interrupts If EA e 0 no interrupt will be acknowledged If EA e 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit IE 6 (reserved) IE 5 (reserved) ES IE 4 Serial Channel interrupt enable ET1 IE 3 Internal Timer Counter 1 Overflow Interrupt EX1 IE 2 External Interrupt Request 1 ET0 IE 1 Internal Timer Counter 0 Overflow Interrupt EX0 IE 0 External Interrupt Request 0 33 UPI-452 Interrupt Priority SFR (IP) A priority level of 0 or 1 may be assigned to each interrupt source with 1 being higher priority level through the IP and the IEP (Interrupt Enable and Priority) SFR A priority level of 1 interrupt can interrupt a priority level 0 service routine to allow nesting of interrupts Symbolic Physical Address Address IP PS PT1 PX1 PT0 PX0 0B8H (MSB) (LSB) Priority Within Symbol Position Function A Level (lowest) IP 7 (reserved) IP 6 (reserved) IP 5 (reserved) PS IP 4 Local Serial Channel 07 PT1 IP 3 Internal Timer Counter 1 05 PX1 IP 2 External Interrupt Request 1 03 PT0 IP 1 Internal Timer Counter 0 01 PX0 IP 0 External Interrupt Request 0 00 (highest) Interrupt Enable and Priority SFR (IEP) The Interrupt Enable and Priority Register establishes the enabling and priority of those resources not covered in the Interrupt Enable and Interrupt Priority SFRs Symbolic Physical Address Address IEP PFIFO EDMA0 EDMA1 PDMA0 PDMA1 EFIFO 0F8H (MSB) (LSB) Priority Symbol Position Function Within a Level IEP 7 (reserved) IEP 6 (reserved) PFIFO IEP 5 FIFO Slave Bus Interface Interrupt Priority 06 EDMA0 IEP 4 DMA Channel 0 Interrupt Enable EDMA1 IEP 3 DMA Channel 1 Interrupt Enable PDMA0 IEP 2 DMA Channel 0 Priority 02 PDMA1 IEP 1 DMA Channel 1 Priority 04 EFIFO IEP 0 FIFO Slave Bus Interface Interrupt Enable 34 UPI-452 FIFO-EXTERNAL HOST INTERFACE Special Function Registers and their default power FIFO DMA FREEZE MODE on reset values SFR Name Label Value Overview Channel Boundary Pointer CBP 40H 64D During FIFO DMA Freeze Mode the internal CPU Output Channel Read Pointers ORPR 40H 64D can reconfigure the FIFO interface FIFO DMA Output Channel Write Pointers OWPR 40H 64D Freeze Mode is provided to prevent the Host from Input Channel Read Pointers IRPR 00H 00D accessing the FIFO during a reconfiguration se- Input Channel Write Pointers IWPR 00H 00D quence The internal CPU invokes FIFO DMA Input Threshold ITHR 80H 128D Freeze Mode by clearing bit 3 of the Slave Control Output Threshold OTHR 01H 1D SFR (SC3) INTRQ becomes active whenever FIFO DMA Freeze Mode is invoked to indicate the freeze status The interrupt can only be deactivated by the The Input and Output FIFO channels can be recon- Host reading the Host Status SFR figured by programming any of these SFRs while the UPI-452 is in the Freeze Mode The Host is notified During FIFO DMA Freeze Mode only two operations when the Freeze Mode is active by a ‘‘1’’ in HST1 of are possible by the Host to the UPI-452 slave the the Host Status Register (HSTAT) The Host should balance are disabled as shown in Table 8 The in- interrogate HST1 to determine the status of the ternal DMA is disabled during FIFO DMA Freeze FIFO interface following reset before attempting to Mode and the internal CPU has write access to all read from or write to the UPI-452 FIFO buffer of the FIFO control SFRs (Table 9) NOTE During the initialization sequence of the UPI-452 Initialization FIFO SFRs the OTHR should be changed from the default setting of 1 to a value between 2 and At power on reset the FIFO Host interface is auto- (80H-CBP)-1 Please refer to the section on Input matically frozen The Slave Control Enable FIFO and Output FIFO threshold SFRs for further infor- DMA Freeze Mode bit defaults to FIFO DMA Freeze mation Mode (SLCON FRZ e 0) Below is a list of the FIFO Table 8 Slave Bus Interface Status During FIFO DMA Freeze Mode Interface Pins Operation In Status In CS A2 A1 A0 READ WRITE DACK Normal Mode FIFO DMA Freeze Mode 1 0 0 1 0 0 1 Read Host Status SFR Operational 1 0 0 1 1 0 1 Read Host Control SFR Operational 1 0 0 1 1 1 0 Write Host Control SFR Disabled 1 0 0 0 0 0 1 Data or DMA Data from Disabled Output Channel 1 0 0 0 0 1 0 Data or DMA Data to Disabled Input Channel 1 0 0 0 1 0 1 Data Stream Command from Disabled Output Channel 1 0 0 0 1 1 0 Data Stream Command to Disabled Input Channel 1 0 1 0 0 0 1 Read Immediate Command Disabled Out from Output Channel 1 0 1 0 0 1 0 Write Immediate Command Disabled In to Input Channel 0 X X X X 0 1 DMA Data from Output Disabled Channel 0 X X X X 1 0 DMA Data to Input Channel Disabled 35 UPI-452 The UPI-452 can also be programmed to interrupt FIFO DMA Freeze Mode without first stopping the the Host following power on reset in order to indi- external Host from accessing the UPI-452 will not cate to the Host that FIFO DMA Freeze Mode is in guarantee a clean break with the external Host progress This is done by enabling the INTRQ inter- rupt output pin via the MODE SFR (MD4) before the The proper way to invoke FIFO DMA Freeze Mode is Slave Control SFR Enable FIFO DMA Freeze Mode by issuing an Immediate Command to the external bit is set to Normal Mode At power on reset the host indicating that FIFO DMA Freeze Mode will be Mode SFR is forced to zero This disables all inter- invoked Upon receiving the Immediate Command rupt and DMA output pins (INTRQ DRQIN the external Host should complete servicing all INTRQIN and DRQOUT INTRQOUT) Because the pending interrupts and DMA requests then send an Host Status SFR FIFO DMA Freeze Mode In Prog- Immediate Command back to the UPI-452 acknowl- ress bit is set a Request For Service INTRQ inter- edging the FIFO DMA Freeze Mode request After rupt is pending until the Host Status SFR is read issuing the first Immediate Command the internal This is because the FIFO DMA Freeze Mode inter- CPU should not perform any action on the FIFO until rupt is always enabled If the Slave Control FIFO FIFO DMA Freeze Mode is invoked DMA Freeze Mode bit (SLCON FRZ) is set to Nor- mal Mode before the MODE SFR INTRQ bit is en- If FIFO DMA Freeze Mode is invoked without stop- abled the INTRQ output will not go active when the ping the Host during Host transfers only the last two MODE SFR INTRQ bit is enabled if the Host Status bytes of data written into or read from the FIFO will SFR has been read be valid The timing diagram for disabling the FIFO module to the external Host interface is illustrated in The default values for the FIFO and Slave Interface Figure 12 Due to this synchronization sequence the represents minimum UPI-452 internal initialization UPI-452 might not go into FIFO DMA Freeze Mode No specific Special Function Register initialization is immediately after SC3 is cleared A special bit in the required to begin operation of the FIFO Slave Inter- Slave Status Register (SST5) is provided to indicate face The last initialization instruction must always the status of the FIFO DMA Freeze Mode The FIFO set the UPI-452 to Normal Mode This causes the DMA Freeze Mode operations described in this sec- UPI-452 to exit FIFO DMA Freeze Mode and en- tion are only valid after SST5 is cleared ables Host read write access of the FIFO As FIFO DMA Freeze Mode is invoked the DRQIN Following reset either hardware (via the RST pin) or or DRQOUT will be deactivated (stopping the trans- software (via HCON SFR bit HC3) the UPI-452 re- ferring of data) bit 1 of the Host Status SFR will be quires 2 internal machine cycles (24 TCLCL) to up- set (HST1 e 1) and SST5 will be cleared (SST5 e 0) date all internal registers to indicate to the external Host and internal CPU that the slave interface has been frozen After the freeze becomes effective any attempt by the exter- Invoking FIFO DMA Freeze Mode nal Host to access the FIFO will cause the overrun During Normal Operation and underrun bits to be activated (bits HST7 (for reads) or HST3 (for writes)) These two bits HST3 When the UPI-452 is in normal operation FIFO DMA and HST7 will be set (deactivated) after the Host Freeze Mode should not be arbitrarily invoked by Status SFR has been read If INTRQ is used to re- clearing SC3 (SC3 e 0) because the external Host quest service the FIFO interface is frozen upon runs asynchronously to the internal CPU Invoking completion of any Host read or write operation in progress 231428 – 17 Figure 12 Disabling FIFO to Host Slave Interface Timing Diagram 36 UPI-452 External Host writing to the Immediate Command In HCON the Input Channel error condition flag SFR and the Host Control SFR is also inhibited (HST3) will be cleared when the slave bus interface is frozen Writing to these two registers after FIFO DMA Freeze Mode is invoked will also cause HST3 (overrun) to be activat- Input FIFO Pointer Registers ed (HST3 e 0) Similarly reading the Immediate (IRPR IWPR) Command Out Register by the external Host is dis- abled during FIFO DMA Freeze Mode and any at- Once the FIFO module is in FIFO DMA Freeze tempt to do so will cause the clearing (deactivating Mode error flags due to overrun and underrun of the ‘‘0’’) of HST7 bit (underrun) Input FIFO pointers will be disabled Any attempt to create an overrun or underrun condition by changing After the slave bus interface is frozen the internal the Input FIFO pointers would result in an inconsist- CPU can perform the following operations on the ency in performance between the status flag and the FIFO Special Function Registers (these operations threshold counter are allowed only during FIFO DMA Freeze Mode) To enhance the speed of the UPI-452 read opera- For FIFO 1 Changing the Channel tions on the Input FIFO will look ahead by two bytes Reconfiguration Boundary Pointer SFR Hence every time the IRPR is changed during FIFO 2 Changing the Input and DMA Freeze Mode two NOPs need to be executed Output Threshold SFR so that the two byte pipeline can be updated with the new data bytes pointed to by the new IRPR The To Enhance the 3 Writing to the read and write Threshold Counter SFR also needs to change by the Testability pointers of the Input and same number of bytes as the IRPR (increase Threshold Counter if IRPR goes forward or decrease Output FIFO’s if IRPR goes backward) This will ensure that future 4 Writing to and reading the interrupts will still be generated only after a thresh- Host Control SFRs old number of bytes are available (See ‘‘Input and 5 Controlling some bits of Host Output FIFO Threshold SFR’’ section below ) and Slave Status SFRS 6 Reading the Immediate In FIFO DMA Freeze Mode the internal CPU can Command Out SFR and also change the content of IWPR and each change Writing to the Immediate of IWPR also requires an update of the Threshold Comand In SFR Counter SFR Normally the internal CPU cannot write into the In- put FIFO It can however during FIFO DMA Freeze Description of each of these special Mode by first reconfiguring the FIFO as an Output functions are as follows FIFO (Refer to ‘‘Input and Output FIFO Threshold SFR’’ section below) Changing the IRPR to be equal to IWPR generates an empty condition while FIFO Module SFRs During changing IWPR to be equal to IRPR generates a full FIFO DMA Freeze Mode condition The order in which the pointers are written Table 9 summarizes the characteristics of all the determines whether a full or empty condition is gen- FIFO Special Function Registers during normal and erated FIFO DMA Freeze Modes The registers that require special treatment in FIFO DMA Freeze Mode are HCON IWPR IRPR OWPR ORPR HSTAT Output FIFO Pointer SFR SSTAT MIN MOUT SFRs They can be described (ORPR and OWPR) in detail as follows In FIFO DMA Freeze Mode the contents of OWPR can be changed by the internal CPU but each change of OWPR or ORPR requires the Threshold Host Control SFR (HCON) Counter SFR to be updated as described in the next During normal operation this register is written to or section A NOP must be executed whenever a new read by the external Host However in FIFO DMA value is written into ORPR as just described for Freeze Mode (i e SST5 e 0) the UPI-452 internal changes to IRPR As before changing ORPR to be CPU has write access to the Host Control SFR and equal to OWPR will generate an empty condition write operations to this SFR by the external Host will Output FIFO overrun or underrun condition cannot not be accepted If the Host attempts to write to be generated though The FIFO pointers should not be set to a value outside of its range 37 UPI-452 Table 9 FIFO SFR’s Characteristics During FIFO DMA Freeze Mode Normal FIFO DMA Freeze Mode Label Name Operation Operation (SST5 e 1) (SST5 e 0) HCON Host Control Not Accessible Read Write HSTAT Host Status Read Only Read Write 4 SLCON Slave Control Read Write Read Write SSTAT Slave Status Read Only Read Write 4 IEP Interrupt Enable Priority Read Write Read Write MODE Mode Register Read Write Read Write IWPR Input FIFO Write Pointer Read Only Read Write 5 IRPR Input FIFO Read Pointer Read Only Read Write 1 5 OWPR Output FIFO Write Pointer Read Only Read Write 6 ORPR Output FIFO Read Pointer Read Only Read Write 2 6 CBP Channel Boundary Pointer Read Only Read Write 3 IMIN Immediate Command In Read Only Read Write IMOUT Immediate Command Out Read Write Read Write FIN FIFO IN Read Only Read Only CIN COMMAND IN Read Only Read Only FOUT FIFO OUT Read Write Read Write COUT COMMAND OUT Read Write Read Write ITHR Input FIFO Threshold Read Only Read Write OTHR Output FIFO Threshold Read Only Read Write NOTES 1 Writing of IRPR will automatically cause the FIFO IN SFR to load the contents of the Input FIFO from that location 2 Writing to ORPR will automatically cause the IOBL SFR to load the contents of the Output FIFO at that ORPR address 3 Writing to the CBP SFR will cause automatic reset of the four pointers of the Input and Output FIFO channels 4 The internal CPU cannot directly change the status of these registers However by changing the status of the FIFO channels the internal CPU can indirectly change the contents of the status registers 5 Changing the Input FIFO Read Write Pointers also requires that a consistent update of the Input FIFO Threshold Counter SFR 6 Changing the Output FIFO Read Write Pointers also requires that a consistent update of the Output FIFO Threshold Counter SFR 38 UPI-452 Input and Output FIFO Threshold SFR Correspondingly the OTHR should be programmed (ITHR OTHR) in the range from 2 to (80H-CBP)-1 An OTHR value of 1 could result in a failure to set the Output The Input and Output FIFO Threshold SFRs are also FIFO service request after subsequent writes by the programmable by the internal CPU during FIFO DMA UPI-452 have filled the Output FIFO Freeze Mode For proper operation of the Threshold feature the Threshold SFR should be changed only NOTE when the Input and Output FIFO channels are emp- When programming the ITHR SFR the eighth bit ty since they reflect the current number of bytes should be set to 1 (OR’d with 80H) This causes available to read write before an interrupt is gener- HSTAT SFR HST0 e 0 Input FIFO Request For ated Service If ITHR bit 7 e 0 then HSTAT HST0 e 1 Input FIFO Does Not Request Service and no in- Table 10 illustrates the Threshold SFRs range of terrupt will be generated values and the number of bytes to be transferred when the Request For Service Flag is activated Host Status SFR (HSTAT) Table 10 Threshold SFRs Range of Values and Number of Bytes to be Transferred When in FIFO DMA Freeze Mode some bits in the Host Status SFR are forced high and will not reflect ITHR No of Bytes OTHR No of Bytes the new status until the system returns to normal (lower Available to (lower Available to operation The definition of the register in FIFO DMA seven bits) be Written seven bits) be Read Freeze Mode is as follows 0 CBP 2 3 NOTE 1 CBP-1 3 4 The internal CPU reads this shadow latch value 2 CBP-2   when reading the Host Status SFR The shadow     latch will keep the information for these bits so nor-     mal operation can be resumed with the right status   (80H-CBP)-3 (80H-CBP)-2 The following bits are set ( e 1) when FIFO DMA CBP-3 3 (80H-CBP)-2 (80H-CBP)-1 Freeze Mode is invoked (80H-CBP)-1 (80H-CBP) HST7 Output FIFO Error Condition Flag 1 e No error The eighth bit of the Input and Output FIFO Thresh- old SFR indicates the status of the service requests 0 e An invalid read has been done on the regardless of the freeze condition If the eighth bit is output FIFO or the Immediate Command a ‘‘1’’ the FIFO is requesting service from the exter- Out Register by the host CPU nal Host In other words when the Threshold SFR value goes below zero (2’s complement) a service NOTE request is generated The 8th bit of the ITHR SFR The normal underrun error condition status is dis- must be set during initialization if the Host interrupt abled If an Immediate Command Out (IMOUT) request is desired immediately upon leaving Freeze SFR read is attempted during FIFO DMA Freeze Mode Normally the ITHR SFR is decremented after Mode the contents of the IMOUT SFR is output on each external Host write to the Input FIFO and incre- the Data Buffer and the error status is cleared mented after each internal CPU read of the Input ( e 0) FIFO The OTHR SFR is decremented by internal HST6 Immediate Command Out SFR Status CPU writes and incremented by external Host reads During normal operation this bit is cleared Thus if the pointers are moved when the FIFO’s are ( e 0) when the IMOUT SFR is written by the not empty these relationships can be used to calcu- UPI-452 internal CPU and set ( e 1) when the late the offset for the Threshold SFRs It is best to IMOUT SFR is read by the external Host change the Threshold SFRs only when the FIFO’s Once the host-slave interface is frozen (i e are empty to avoid this complication The threshold SST5 e 0) this bit will be read as a 1 by the registers should also be updated after the pointers host CPU A shadow latch will keep the infor- have been manipulated mation for this bit so normal operation can be resumed with the correct status NOTE The ITHR should only be programmed in the range Shadow latch from 0 to (CBP-3) An ITHR value of (CBP-2) could 1 e Internal CPU reads the IMOUT SFR result in a failure to set the Input FIFO service re- 0 e Internal CPU writes to the IMOUT SFR quest signal after the Input FIFO has been emptied 39 UPI-452 HST5 Data Stream Command at Output FIFO Slave Status SFR (SSTAT) This bit is forced to a ‘‘1’’ during FIFO DMA Freeze Mode to prevent the external host The Slave Status SFR is a read-only SFR However CPU from trying to read the DSC Once nor- once the slave interface is frozen most of the bits of mal operation is resumed HST5 will reflect this SFR can be changed by the internal CPU by the Data Command status of the current byte reconfiguring the FIFO and accessing the FIFO Spe- in the Output FIFO cial Function Registers Shadow Latch (read by the internal CPU) SST7 Output FIFO Overrun Error Flag 1 e No Data Stream Command (DSC) Inoperative in FIFO DMA Freeze Mode 0 e Data Stream Command at Output FIFO SST6 Immediate Command Out SFR Status HST4 Output FIFO Service Request Status In FIFO DMA Freeze Mode this bit will be cleared when the internal CPU reads the Im- When FIFO DMA Freeze Mode is invoked mediate Command Out SFR and set when this bit no longer reflects the Output FIFO Re- the internal CPU writes to the Immediate quest Service Status This bit wll be forced to Command Out Register a ‘‘1’’ SST5 FIFO-External Interface FIFO DMA Freeze HST3 Input FIFO Error Condition Flag Mode Status 1 e No error This bit indicates to the internal CPU that 0 e One of the following operations has FIFO DMA Freeze Mode is in progress and been attempted by the external host and that it has write access to the FIFO Control is invalid Host control and Immediate Command SFRs 1) Write into the Input FIFO SST4 Output FIFO Request Service Status 2) Write into the Host Control SFR During normal operation this bit indicates to 3) Write into the Immediate Command In the internal CPU that the Output FIFO is SFR ready for more data The status of this bit re- flects the position of the Output FIFO read NOTE and write pointers Hence in FIFO DMA The normal Input FIFO overrun condition is dis- Freeze Mode this flag can be changed by the abled internal CPU indirectly as the read and write pointers change HST2 Immediate Command In SFR Status SST3 Input FIFO Underrun Flag This bit is normally cleared when the internal CPU reads the IMIN SFR and set when the Inoperative during FIFO DMA Freeze Mode external host CPU writes into the IMIN SFR During normal operation a read operation When the host-slave interface is frozen read- clears ( e 0) this bit when there are no data ing and writing of the IMIN by the internal bytes in the Input FIFO and deactivated ( e 1) CPU will change the shadow latch of this bit when the Slave Status SFR is read In FIFO This bit will be read as a ‘‘1’’ by the external DMA Freeze Mode this bit will not be cleared Host by an Input FIFO read underrun error condi- Shadow latch tion nor will it be reset by the reading of the Slave Status SFR 1 e Internal CPU writes into IMIN SFR SST2 Immediate Command In SFR Status 0 e Internal CPU reads the IMIN SFR This bit is normally activated ( e 0) when the HST1 FIFO DMA Freeze Mode Status external host CPU writes into the Immediate 1 e FIFO DMA Freeze Mode Command In SFR and deactivated ( e 1) 0 e Normal Operation (non-FIFO DMA when it is read by the internal CPU In FIFO Freeze Mode) DMA Freeze Mode this bit will not be activat- ed ( e 0) by the external Host’s writing of the NOTE Immediate Command IN SFR since this func- This bit is used to indicate to the external Host that tion is disabled However this bit will be the host-slave interface has been frozen and hence cleared ( e 0) if the internal CPU writes to the the external Host functions are now reduced as Immediate Command In SFR and it will be set shown in Table 8 e 1) if it reads from the register HST0 Input FIFO Request Service Satus When slave interface is frozen this bit no longer reflects the Input FIFO Request Serv- ice Status This bit will be forced to a ‘‘1’’ 40 UPI-452 SST1 Data Stream Command at Input FIFO Flag ORPR SFR to zero This generates a FIFO empty In FIFO DMA Freeze Mode this bit operates signal and allows internal CPU write operations to all normally It indicates whether the next byte of 128 bytes of the FIFO The Threshold registers also data from the Input FIFO is a DSC or data need to be adjusted when the pointers are changed byte If it is a DSC byte reading from the (See ‘‘Input and Output FIFO Threshold SFR’’ sec- FIFO IN SFR will result in reading invalid data tion below ) (FFH) and vice versa In FIFO DMA Freeze Mode this bit still reflects the type of data byte available from the Input FIFO MEMORY ORGANIZATION SST0 Input FIFO Service Request Flag The UPI-452 has separate address spaces for Pro- During normal operation this bit is activated gram Memory and Data Memory like the 80C51 The ( e 0) when the Input FIFO contains bytes that Program Memory can be up to 64K bytes The lower can be read by the internal CPU and deacti- 8K of Program Memory may reside on-chip The vated ( e 1) when the Input FIFO does not Data Memory consists of 256 bytes of on-chip RAM need any service from the internal CPU In up to 64K bytes of off-chip RAM and a number of FIFO DMA Freeze Mode the status of this bit ‘‘SFRs’’ (Special Function Registers) which appear should not change unless the pointers of the as yet another set of unique memory addresses Input FIFO are changed In this mode the in- Table 11a Internal Memory Addressing ternal CPU can indirectly change this bit by changing the read and write pointers of the Memory Space Addressing Method Input FIFO but cannot change it directly Lower 128 Bytes of Direct or Indirect Internal RAM Immediate Command In Out SFR Upper 128 Bytes Indirect Only (IMIN IMOUT) of Internal RAM If FIFO DMA Freeze Mode is in progress writing to UPI-452 SFR’s Direct Only the Immediate Command In SFR by the external host will be disabled and any such attempt will The 80C51 Special Function Registers are listed in cause HST3 to be cleared ( e 0) Similarly the Imme- Table 11a and the additional UPI-452 SFRs are list- diate Command Out SFR read operation (by the ed in Table 11b A brief description of the 80C51 host) will be disabled internally and read attempts core SFRs is also provided below will cause HST7 to be cleared ( e 0) Accessing External Memory Internal CPU Read and Write of the FIFO During FIFO DMA Freeze Mode As in the 80C51 accesses to external memory are of two types Accesses to external Program Memory In normal operation the Input FIFO can only be read and accesses to external Data Memory by the internal CPU and similarly the Output FIFO can only be written by the internal CPU During FIFO External Program Memory is accessed under two DMA Freeze Mode the internal CPU can read the conditions entire contents of the Input FIFO by programming 1) Whenever signal EA e 0 or the CBP SFR to 7FH setting the IRPR SFR to zero and then the IWPR SFR to zero Programming the 2) Whenever the program counter (PC) contains a pointer registers in this order generates a FIFO full number that is larger than 1FFFH signal to the FIFO logic and enables internal CPU read operations If the IWPR and IRPR are already This requires that the ROMless versions have EA zero the write pointer should be changed to a non- wired low to enable the lower 8K program bytes to zero value to clear the empty status then the point- be fetched from external memory ers can be set to zero Writing to the IRDR SFR automatically updates the look ahead registers External Data Memory is accessed using either the MOVX DPTR (16 bit address) or the MOVX Ri (8 In a similar manner the internal CPU can write to all bit address) instructions or during external data 128 bytes of the FIFO by setting the CBP SFR to memory transfers zero setting OWPR SFR to zero and then setting 41 UPI-452 Table 11b 80C51 Special Function Registers Table 11c UPI-452 Additional Special Symbol Name Address Contents Function Registers (Continued) ACC Accumulator 0E0H 00H Symbol Name Address Contents B B Register 0F0H 00H DARL0 Low Byte 0C2H I PSW Program Status 0D0H 00H DARH0 Hi Byte 0C3H I Word Channel 0 SP Stack Pointer 81H 07H DPTR Data Pointer 82H 0000H DARL1 Low Byte 0D2H I (consisting of DPH DARH1 Hi Byte 0D3H I and DPL) Channel 1 P0 Port 0 80H 0FFH DCON0 DMA0 Control 92H 00H P1 Port 1 90H 0FFH P2 Port 2 0A0H 0FFH DCON1 DMA1 Control 93H 00H P3 Port 3 0B0H 0FFH FIN FIFO IN 0EEH I IP Interrupt Priority 0B8H 0E0H FOUT FIFO OUT 0FEH I Control IE Interrupt Enable 0A8H 60H HCON Host Control 0E7H 00H Control HSTAT Host Status 0E6H 0FBH TMOD Timer Counter 89H 00H IEP Interrupt Enable 0F8H 0C0H Mode Control and Priority TCON Timer Counter 88H 00H Control IMIN Immediate Command 0FCH I TH0 Timer Counter 8CH 00H In 0 (high byte) IMOUT Immediate Command 0FDH I TL0 Timer Counter 8AH 00H Out 0 (low byte) IRPR Input Read 0EBH 00H TH1 Timer Counter 8DH 00H Pointer 1 (high byte) TL1 Timer Counter 8BH 00H ITHR Input FIFO 0F6H 80H 1 (low byte) Threshold SCON Serial Control 98H 00H IWPR Input Write 0EAH 00H SBUF Serial Data Buff 99H I Pointer PCON Power Control 87H I0H MODE Mode Register 0F9H 8FH I e Indeterminate The SFRs marked with an asterisk ( ) are both bit- and ORPR Output Read 0FAH 40H byte- addressable The functions of the SFRs are as fol- Pointer lows OTHR Output FIFO 0F7H 01H Table 11c UPI-452 Additional Threshold Special Function Registers OWPR Output Write 0FBH 40H Symbol Name Address Contents Threshold BCRL0 DMA Byte 0E2H I P4 Port 4 0C0H 0FFH Count Low Byte DMA Source Address BCRH0 High Byte 0E3H I SARL0 Low Byte 0A2H I Channel 0 SARH0 Hi Byte 0A3H I BCRL1 Low Byte 0F2H I Channel 0 BCRH1 Hi Byte 0F3H I SARL1 Low Byte 0B2H I Channel 1 SARH1 Hi Byte 0B3H I CBP Channel Boundary 0ECH 40H Channel 1 Pointer CIN COMMAND IN 0EFH I SLCON Slave Control 0E8H 04H COUT COMMAND OUT 0FFH I SSTAT Slave Status 0E9H 08FH DMA Destination I e Indeterminate Address The SFRs marked with an asterisk ( ) are both bit- and byte- addressable The functions of the SFRs are as fol- lows 42 UPI-452 Miscellaneous Special Function DATA POINTER Register Description The Data Pointer (DPTR) consists of a high byte 80C51 SFRs (DPH) and a low byte (DPL) Its intended function is to hold a 16-bit address It may be manipulated as a 16-bit register or as two independent 8-bit registers ACCUMULATOR ACC is the Accumuator SFR The mnemonics for PORTS 0 TO 4 accumulator-specific instructions however refer to the accumulator simply as A P0 P1 P2 P3 and P4 are the SFR latches of Ports 0 1 2 3 and 4 respectively B REGISTER SERIAL DATA BUFFER The B SFR is used during multiply and divide opera- The Serial Data Buffer is actually two separate regis- tions For other instructions it can be treated as an- ters a transmit buffer and a receive buffer register other scratch pad register When data is moved to SBUF it goes to the transmit buffer where it is held for serial transmission (Mov- ing a byte to SBUF is what initiates the transmis- PROGRAM STATUS WORD sion ) When data is moved from SBUF it comes from the receive buffer The PSW SFR contains program status information as detailed in Table 12 TIMER COUNTER SFR STACK POINTER Register pairs (TH0 TL0) and (TH1 TL1) are the 16-bit counting registers for Timer Counters 0 and 2 The Stack Pointer register is 8 bits wide It is incre- mented before data is stored during PUSH and CALL executions While the stack may reside any- POWER CONTROL SFR (PCON) where in on-chip RAM the Stack Pointer is initialized to 07H after a reset This causes the stack to begin The PCON Register (Table 13) controls the power at location 08H down and idle modes in the UPI-452 as well as pro- viding the ability to double the Serial Channel baud rate There are also two general purpose flag bits available to the user Bits 5 and 6 are used to set the HOLD HOLD Acknowledge mode (see ‘‘General Purpose DMA Channels’’ section) and bit 4 is not used 43 UPI-452 Table 12 Program Status Word Symbolic Physical Address Address PSW CY AC FO RS1 RS0 OV P 0D0H (MSB) (LSB) Symbol Position Name CY PSW 7 Carry Flag AC PSW 6 Auxiliary Carry (For BCD operations) F0 PSW 5 Flag 0 (user assignable) RS1 PSW 4 Register Bank Select bit 1 RS0 PSW 3 Register Bank Select bit 0 OV PSW 2 Overflow Flag PSW 1 (reserved) P PSW 0 Parity Flag (RS1 RS0) enable internal RAM register banks as follows RS1 RS0 Internal RAM Register Bank 0 0 Bank 0 0 1 Bank 1 1 0 Bank 2 1 1 Bank 3 Table 13 PCON Special Function Register Symbolic Physical Address Address PCON SMOD ARB REQ GF1 GF0 PD IDL 087H (MSB) (LSB) Symbol Position Function SMOD PCON7 Double Baud rate bit When set to a 1 the baud rate is doubled when the serial port is being used in either Mode 1 2 or 3 ARB PCON6 HLD HLDA Arbiter control bit REQ PCON5 HLD HLDA Requestor control bit PCON4 (reserved) GF1 PCON3 General-purpose flag bit GF0 PCON2 General-purpose flag bit PD PCON1 Power Down bit Setting this bit activates power down operation IDL PCON0 Idle Mode bit Setting this bit activates idle mode operation See ‘‘Ext Memory DMA’’ description NOTE If 1’s are written to PD and IDL at the same time PD takes precedence The reset value of PCON is (000X0000) 44 UPI-452 ABSOLUTE MAXIMUM RATINGS NOTICE This is a production data sheet The specifi- cations are subject to change without notice Ambient Temperature Under Bias 0 C to 70 C WARNING Stressing the device beyond the ‘‘Absolute Storage Temperature b 65 C to a 150 C Maximum Ratings’’ may cause permanent damage Voltage on Any These are stress ratings only Operation beyond the Pin to VSS b 0 5V to VCC a 0 5V ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ Voltage on VCC to VSS b 0 5V to a 6 5V may affect device reliability Power Dissipation 1 0W D C CHARACTERISTICS TA e 0 C to 70 C VCC e 5V g 10% VSS e 0V Symbol Parameter Min Max Units Test Conditions VIL Input Low Voltage b0 5 08 V VIH Input High Voltage 20 VCC a 0 5 V (except XTAL1 RST) VIH1 Input High Voltage 39 VCC a 0 5 V (XTAL1 RST) VOL Output Low Voltage 0 45 V IOL e 1 6 mA (Note 1) (Ports 1 2 3 4) VOL1 Output Low Voltage 0 45 V IOL e 3 2 mA (Note 1) (except Ports 1 2 3 4) VOH Output High Voltage 24 V IOH e b 60 mA VCC e 5V g 10% (Ports 1 2 3 4) 0 9 VCC V IOH e b 10 mA VOH1 Output High Voltage 24 V IOH e b 400 mA VCC e 5V g 10% (except Ports 1 2 3 4 and 0 9 VCC V IOH e b 40 mA (Note 2) Host Interface (Slave) Port) VOH2 Output High Voltage 24 V IOH e b 400 mA VCC e 5V g 10% (Host Interface (Slave) Port) V b 0 4 CC V IOH e b 10 mA IIL Logical 0 Input Current b 50 mA VIN e 0 45V (Ports 1 2 3 4) ITL Logical 1 to 0 Transition b 650 mA VIN e 2V Current (Ports 1 2 3 4) 45 UPI-452 D C CHARACTERISTICS TA e 0 C to 70 C VCC e 5V g 10% VSS e 0V (Continued) Symbol Parameter Min Max Units Test Conditions ILI Input Leakage Current g 10 mA 0 45V k VIN k VCC (except Ports 1 2 3 4) IOZ Output Leakage Current g 10 mA 0 45V k VOUT k VCC (except Ports 1 2 3 4) ICC Operating Current 50 mA VCC e 5 5V 14 MHz (Note 4) ICCI Idle Mode Current 25 mA VCC e 5 5V 14 MHz (Note 5) IPD Power Down Current 100 mA VCC e 2V (Note 3) RRST Reset Pulldown Resistor 50 150 KX CIO Pin Capacitance 20 pF 1 MHz TA e 25 C (sampled not tested on all parts) NOTES 1 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1- to-0 transitions during bus operations In the worst cases (capacitive loading l 100 pF) the noise pulse on the ALE line may exceed 0 8V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt Trigger STROBE input 2 Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall before the 0 9 VCC specification when the address bits are stabilizing 3 Power DOWN ICC is measured with all output pins disconnected EA e Port 0 e VCC XTAL2 N C RST e VSS DB e VCC WR e RD e DACK e CS e A0 e A1 e A2 e VCC Power Down Mode is not supported on the 87C452P 4 ICC is measured with all output pins disconnected XTAL1 driven with TCLCH TCHCL e 5 ns VIL e VSS a 0 5V VIH e VCC b 0 5V XTAL2 N C EA e RST e Port 0 e VCC WR e RD e DACK e CS e A0 e A1 e A2 e VCC ICC would be slightly higher if a crystal oscillator is used 5 Idle ICC is measured with all output pins disconnected XTAL1 driven with TCLCH TCHCL e 5 ns VIL e VSS a 0 5V VIH e VCC b 0 5V XTAL2 N C Port 0 e VCC EA e RST e VSS WR e RD e DACK e CS e A0 e A1 e A2 e VCC EXPLANATION OF THE AC SYMBOLS Q Output data R READ signal Each timing symbol has 5 characters The first char- T Time acter is always a ‘T’ (stands for time) The other characters depending on their positions stand for V Valid the name of a signal or the logical status of that W WRITE signal signal The following is a list of all the characters and X No longer a valid logic level what they stand for Z Float A Address C Clock EXAMPLE D Input data H Logic level HIGH TAVLL e Time for Address Valid to ALE Low I Instruction (program memory contents) TLLPL e Time for ALE Low to PSEN Low L Logic level LOW or ALE P PSEN 46 UPI-452 A C CHARACTERISTICS TA e 0 C to 70 C VCC e 5V g 10% VSS e 0V Load Capacitance for Port 0 ALE and PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS 14 MHz Osc Variable Oscillator Symbol Parameter Units Min Max Min Max 1 TCLCL Oscillator Frequency 35 14 MHz TLHLL ALE Pulse Width 103 2TCLCL b 40 ns TAVLL Address Valid to ALE Low 25 TCLCL b 55 ns (Note 1) TLLAX Address Hold after ALE Low 36 TCLCL b 35 ns TLLIV ALE Low to Valid Instr In 185 4TCLCL b 100 ns TLLPL ALE Low to PSEN Low 31 TCLCL b 40 ns TPLPH PSEN Pulse Width 169 3TCLCL b 45 ns TPLIV PSEN Low to Valid Instr In 110 3TCLCL b 105 ns TPXIX Input Instr Hold after PSEN 0 0 ns TPXIZ Input Instr Float after PSEN 57 TCLCL b 25 ns (Note 1) TAVIV Address to Valid Instr In 252 5TCLCL b 105 ns TPLAZ PSEN Low to Address Float 10 10 ns TRLRH RD Pulse Width 329 6TCLCL b 100 ns TWLWH WR Pulse Width 329 6TCLCL b 100 ns TRLDV RD Low to Valid Data In 192 5TCLCL b 165 ns TRHDX Data Hold after RD 0 0 ns TRHDZ Data Float after RD 73 2TCLCL b 70 ns TLLDV ALE Low to Valid Data In 422 8TCLCL b 150 ns TAVDV Address to Valid Data In 478 9TCLCL b 165 ns TLLWL ALE Low to RD or WR Low 164 264 3TCLCL b 50 3TCLCL a 50 ns TAVWL Address Valid to RD or WR Low 156 4TCLCL b 130 ns TQVWX Data Valid to WR Transition 11 TCLCL b 60 ns TWHQX Data Hold after WR 21 TCLCL b 50 ns TRLAZ RD Low to Address Float 0 0 ns TWHLH RD or WR High to ALE High 31 111 TCLCL b 40 TCLCL a 40 ns TQVWH Data Valid to WR (Setup Time) 350 7TCLCL b 150 ns NOTE 1 Use the value of 14 MHz specification or variable oscillator specification whichever is greater 47 UPI-452 EXTERNAL DATA MEMORY READ CYCLE 231428 – 19 EXTERNAL PROGRAM MEMORY READ CYCLE 231428 – 20 48 UPI-452 EXTERNAL DATA MEMORY WRITE CYCLE 231428 – 21 SHIFT REGISTER MODE TIMING WAVEFORMS 231428 – 22 49 UPI-452 EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1 TCLCL Oscillator Frequency 35 14 MHz TCHCX High Time 20 ns TCLCX Low Time 20 ns TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns NOTE External clock timings are sampled not tested on all parts SERIAL PORT TIMING SHIFT REGISTER MODE Test Conditions TA e 0 C to 70 C VCC e 5V g 10% VSS e 0V Load Capacitance e 80 pF 14 MHz Osc Variable Oscillator Symbol Parameter Units Min Max Min Max TXLXL(1) Serial Port Clock Cycle Time 857 12TCLCL ns TQVXH Output Data Setup to Clock Rising Edge 581 10TCLCL b 133 ns TXHQX Output Data Hold after Clock Rising Edge 26 2TCLCL b 117 ns TXHDX Input Data Hold after Clock Rising Edge 0 0 ns TXHDV Clock Rising Edge to Input Data Valid 581 10TCLCL b 133 ns NOTE 1 The tolerance of this signal is a function of the input oscillator frequency (TXLXL e 12TCLCL) EXTERNAL CLOCK DRIVE WAVEFORM 231428 – 23 AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS 231428 – 24 231428 – 25 AC inputs during testing are driven at VCC b 0 5V for a logic ‘‘1’’ For timing purposes a port pin is no longer floating when a and 0 45V for a logic ‘‘0’’ Timing measurements are made at VIH 100 mV change from load voltage occurs and begins to float min for a logic ‘‘1’’ and VIL max for a logic ‘‘0’’ when a 100 mV change from the loaded VOH VOL level occurs IOL IOH t g 20 mA 50 UPI-452 HLD HLDA WAVEFORMS Arbiter Mode 231428 – 26 Requestor Mode 231428 – 31 HLD HLDA TIMINGS Test Conditions TA e 0 C to a 70 C VCC e 5V g 10% VSS e 0V Load Capacitance e 80 pF 14 MHz Osc Variable Oscillator Symbol Parameter Units Min Max Min Max THMIN HLD Pulse Width 386 4TCLCL a 100 ns THLAL HLD to HLDA Delay if 186 672 4TCLCL b 100 8TCLCL a 100 ns HLDA is Granted THHAH HLD to HLDA Delay 186 672 4TCLCL b 100 8TCLCL a 100 ns TAMIN HLDA Pulse Width 386 4TCLCL a 100 ns TAHHL HLDA Inactive to 186 4TCLCL b 100 ns HLD Active 51 UPI-452 HOST PORT WAVEFORMS 231428 – 27 HOST PORT TIMINGS Test Conditions TA e 0 C to 70 C VCC e 5V g 10% VSS e 0V Load Capacitance e 80 pF 14 MHz Osc Variable Oscillator Symbol Parameter Units Min Max Min Max TCC Cycle Time 429 6TCLCL ns TPW Command Pulse Width 100 100 ns TRV Recovery Time 60 60 ns TAS Address Setup Time 5 5 ns TAH Address Hold Time 30 30 ns TDS WRITE Data Setup Time 30 30 ns TDHW WRITE Data Hold Time 5 5 ns TDHR READ Data Hold Time 7 40 7 40 ns TDV READ Active to Read 92 92 ns Data Valid Delay TDR WRITE Inactive to Read 343 4 8TCLCL ns Data Valid Delay (Applies only to Host Control SFR) TRQ READ or WRITE Active 150 150 ns to DRQIN or DRQOUT Inactive Delay 52 UPI-452 REVISION HISTORY DOCUMENT UPI-452 Data Sheet OLD REVISION NUMBER 231428-005 NEW REVISION NUMBER 231428-006 1 Maximum Clock Rate was changed from 16 MHz to 14 MHz This change is reflected in all Maximum Timing specifications 2 The proper range of values for ITHR has been changed from 0 to (CBP-2) to 0 to (CBP-3) to ensure proper setting of the Input FIFO request for service bit See the following sections INPUT FIFO CHANNEL and INPUT AND OUTPUT FIFO THRESHOLD SFR (ITHR OTHR) 3 The proper range of values for OTHR has been changed from 1 to (80H-CBP)-1 to 2 to (80-CBP)-1 to ensure proper setting of the Output FIFO request for service bit See the following sections OUTPUT FIFO CHANNEL FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE and INPUT AND OUT- PUT FIFO THRESHOLD SFR (ITHR OTHR) 4 The following D C Characteristics were deleted from the data sheet VOH e 0 75 VCC IOH e b 25 mA VOH1 e 0 75 VCC IOH e 150 mA VOH2 e 3 0V IOH e 1 mA and ICC1 e 15 mA VCC e 5 5V (87C452P) See D C CHARACTERISTICS TABLE 5 The parameter descriptions for THHAH and THLAL has been reversed and their maximum specification for clock rates less than 14 MHz has been changed from 4TCLC a 100 ns to 8TCLC a 100 ns See HLD HLDA TIMINGS 6 TAMIN specification has been removed from the Arbiter Mode waveform diagram and added to the Request- or Mode waveform diagram See HLD HLDA WAVEFORMS 7 Minimum TDHR timing changed from 5 ns to 7 ns 53