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Source PDF: /mnt/fw-js/docs/Hardware/Intel/Intel 8741A Universal Peripheral Interface.pdf Like all conversions the text below should be fully readable as UTF-8 unicode text. --------------------------------------------------------------- 8741A UNIVERSAL PERIPHERAL INTERFACE 8-BIT MICROCOMPUTER Y 8-Bit CPU plus ROM RAM I O Timer Y Fully Compatible with All and Clock in a Single Package Microprocessor Families Y One 8-Bit Status and Two Data Y 3 6 MHz 8741A-8 Available Registers for Asynchronous Slave-to- Y Expandable I O Master Interface Y RAM Power-Down Capability Y DMA Interrupt or Polled Operation Supported Y Over 90 Instructions 70% Single Byte Y 1024 x 8 EPROM 64 x 8 RAM 8-Bit Y Available in EXPRESS Timer Counter 18 Programmable I O Standard Temperature Range Pins Extended Temperature Range The Intel 8741A is a general purpose programmable interface device designed for use with a variety of 8-bit microprocessor systems It contains a low cost microcomputer with program memory data memory 8-bit CPU I O ports timer counter and clock in a single 40-pin package Interface registers are included to enable the UPI device to function as a peripheral controller in MCS -48 MCS-80 MCS-85 MCS-86 and other 8-bit systems The UPI-41A has 1K words of program memory and 64 words of data memory on-chip The device has two 8-bit TTL compatible I O ports and two test inputs Individual port lines can function as either inputs or outputs under software control I O can be expanded with the 8243 device which is directly compatible and has 16 I O lines An 8-bit programmable timer counter is included in the UPI device for generating timing sequences or counting external inputs Additional UPI features include single 5V supply single-step mode for debug and dual working register banks Because it’s a complete microcomputer the UPI provides more flexibility for the designer than conventional LSI interface devices It is designed to be an efficient controller as well as an arithmetic processor Applica- tions include keyboard scanning printer control display multiplexing and similar functions which involve inter- facing peripheral devices to microprocessor systems Pin Configuration 290241 – 2 October 1989 Order Number 290241-001 1 8741A Block Diagram 290241 – 1 Table 1 Pin Description Signal Description Signal Description D 0 – D7 Three-state bidirectional DATA BUS BUFFER XTAL 1 Inputs for a crystal LC or an external timing (BUS) lines used to interface the UPI-41A to an 8-bit XTAL 2 signal to determine the internal oscillator master system data bus frequency P10 – P17 8-bit PORT 1 quasi-bidirectional I O lines SYNC Output signal which occurs once per UPI-41A instruction cycle SYNC can be used as a strobe P20 – P27 8-bit PORT 2 quasi-bidirectional I O lines The for external circuitry it is also used to lower 4 bits (P20 – P23) interface directly to the synchronize single step operation 8243 I O expander device and contain address and data information during PORT 4–7 access EA External access input which allows emulation The upper 4 bits (P24 – P27) can be programmed testing and PROM verification to provide interrupt Request and DMA PROG Multifunction pin used as the program pulse Handshake capability Software control can input during PROM programming configure P24 as OBF (Output Buffer Full) P25 as IBF (Input Buffer Full) P26 as DRQ (DMA During I O expander access the PROG pin acts Request) and P27 as DACK (DMA as an address data strobe to the 8243 ACKnowledge) RESET Input used to reset status flip-flops and to set WR I O write input which enables the master CPU to the program counter to zero write data and command words to the UPI-41A RESET is also used during PROM programming INPUT DATA BUS BUFFER and verification RESET should be held low for a minimum of 8 RD I O read input which enables the master CPU to instruction cycles after power-up read data and status words from the OUTPUT DATA BUS BUFFER or status register SS Single step input used in the 8741A in conjunction with the SYNC output to step the CS Chip select input used to select one UPI-41A out program through each instruction of several connected to a common data bus VCC a 5V main power supply pin A0 Address input used by the master processor to indicate whether byte transfer is data or VDD a 5V during normal operation a 25V during command During a write operation flag F1 is set programming operation Low power standby to the status of the A0 input supply pin in ROM version TEST 0 Input pins which can be directly tested using VSS Circuit ground potential TEST 1 conditional branch instructions (T1) also functions as the event timer input (under software control) T0 is used during PROM programming and verification in the 8741A 2 2 8741A UPI-41A FEATURES AND If ‘‘EN FLAGS’’ has been executed P25 becomes the IBF (Input Buffer Full) pin A ‘‘1’’ written to P25 ENHANCEMENTS enables the IBF pin (the pin outputs the inverse of 1 Two Data Bus Buffers one for input and one for the IBF Status Bit) A ‘‘0’’ written to P25 disables output This allows a much cleaner Master Slave the IBF pin (the pin remains low) This pin can be protocol used to indicate that the UPI is ready for data 290241 – 4 Data Bus Buffer Interrupt Capability 290241 – 3 EN FLAGS Op Code 0F5H 2 8 Bits of Status 1 1 1 1 0 1 0 1 ST7 ST6 ST5 ST4 F1 F0 IBF OBF D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 5 P26 and P27 are port pins or DMA handshake pins for use with a DMA controller These pins default ST4 –ST7 are user definable status bits These to port pins on Reset bits are defined by the ‘‘MOV STS A’’ single byte single cycle instruction Bits 4–7 of the accumula- If the ‘‘EN DMA’’ instruction has been executed tor are moved to bits 4–7 of the status register P26 becomes the DRQ (DMA Request) pin A ‘‘1’’ Bits 0–3 of the status register are not affected written to P26 causes a DMA request (DRQ is acti- MOV STS A Op Code 90H vated) DRQ is deactivated by DACK # RD DACK # WR or execution of the ‘‘EN DMA’’ in- 1 0 0 1 0 0 0 0 struction If ‘‘EN DMA’’ has been executed P27 becomes D7 D0 the DACK (DMA Acknowledge) pin This pin acts 3 RD and WR are edge triggered IBF OBF F1 and as a chip select input for the Data Bus Buffer reg- INT change internally after the trailing edge of RD isters during DMA transfers or WR 290241 – 5 290241 – 6 4 P24 and P25 are port pins or Buffer Flag pins which can be used to interrupt a master proces- DMA Handshake Capability sor These pins default to port pins on Reset EN DMA Op Code 0E5H If the ‘‘EN FLAGS’’ instruction has been execut- ed P24 becomes the OBF (Output Buffer Full) pin 1 1 1 0 0 1 0 1 A ‘‘1’’ written to P24 enables the OBF pin (the pin outputs the OBF Status Bit) A ‘‘0’’ written to P24 D7 D0 disables the OBF pin (the pin remains low) This pin can be used to indicate that valid data is avail- able from the UPI41A (in Output Data Bus Buffer) 3 3 8741A APPLICATIONS 290241 – 7 290241 – 8 Figure 1 8085A-8741A Interface Figure 2 8048-8741A Interface 290241 – 9 290241 – 10 Figure 3 8741A-8243 Keyboard Scanner Figure 4 8741A Matrix Printer Interface 4 4 8741A PROGRAMMING VERIFYING AND 8 VDD e 25V (programming power) ERASING THE 8741A EPROM 9 PROG e 0V followed by one 50 ms pulse to 23V 10 VDD e 5V Programming Verification 11 TEST 0 e 5V (verify mode) 12 Read and verify data on BUS In brief the programming process consists of acti- 13 TEST 0 e 0V vating the program mode applying an address latching the address applying data and applying a 14 RESET e 0V and repeat from step 6 programming pulse Each word is programmed com- 15 Programmer should be at conditions of step 1 pletely before moving on to the next and is followed when 8741A is removed from socket by a verification step The following is a list of the pins used for programming and a description of their functions 8741A Erasure Characteristics Pin Function The erasure characteristics of the 8741A are such that erasure begins to occur when exposed to light XTAL 1 Clock Input (1 to 6 MHz) with wavelengths shorter than approximately Reset Initialization and Address Latching 4000 Angstroms ( ) It should be noted that sunlight Test 0 Selection of Program or Verify Mode and certain types of fluorescent lamps have wave- EA Activation of Program Verify Modes lengths in the 3000-4000 range Data show that BUS Address and Data Input constant exposure to room level fluorescent lighting Data Output during Verify could erase the typical 8741A in approximately 3 P20–1 Address Input years while it would take approximately one week to VDD Programming Power Supply cause erasure when exposed to direct sunlight If PROG Program Pulse Input the 8741A is to be exposed to these types of lighting conditions for extended periods of time opaque la- WARNING An attempt to program a missocketed 8741A will result in severe dam- bels are available from Intel which should be placed age to the part An indication of a properly socketed part is the ap- over the 8741A window to prevent unintentional era- pearance of the SYNC clock output The lack of this clock may be sure used to disable the programmer The recommended erasure procedure for the 8741A The Program Verify sequence is is exposure to shortwave ultraviolet light which has a 1 A0 e 0V CS e 5V EA e 5V RESET e 0V wavelength of 2537 The integrated dose (i e UV TEST0 e 5V VDD e 5V clock applied or internal intensity c exposure time) for erasure should be a oscillator operating BUS and PROG floating minimum of 15 w-sec cm2 The erasure time with 2 Insert 8741A in programming socket this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12 000 mW cm2 power rat- 3 TEST 0 e 0V (select program mode) ing The 8741A should be placed within one inch of 4 EA e 23V (active program mode) the lamp tubes during erasure Some lamps have a 5 Address applied to BUS and P20–1 filter on their tubes which should be removed before erasure 6 RESET e 5V (latch address) 7 Data applied to BUS 5 5 8741A ABSOLUTE MAXIMUM RATINGS NOTICE This is a production data sheet The specifi- cations are subject to change without notice Ambient Temperature under Bias 0 C to a 70 C WARNING Stressing the device beyond the ‘‘Absolute Storage Temperature b 65 C to a 150 C Maximum Ratings’’ may cause permanent damage Voltage on Any Pin with These are stress ratings only Operation beyond the Respect to Ground 0 5V to a 7V ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ Power Dissipation 1 5W may affect device reliability D C CHARACTERISTICS TA e 0 C to a 70 C VSS 0V VCC e VDD e a 5V g 10% Symbol Parameter Min Max Unit Test Conditions VIL Input Low Voltage (except XTAL1 XTAL2 RESET) b0 5 08 V VIL1 Input Low Voltage (XTAL1 XTAL2 RESET) b0 5 06 V VIH Input High Voltage (except XTAL1 XTAL2 RESET) 22 VCC VIH1 Input High Voltage (XTAL1 XTAL2 RESET) 38 VCC V VOL Output Low Voltage (D0 –D7) 0 45 V IOL e 2 0 mA VOL1 Output Low Voltage (P10P17 P20P27 Sync) 0 45 V IOL e 1 6 mA VOL2 Output Low Voltage (PROG) 0 45 V IOL e 1 0 mA VOH Output High Voltage (D0 –D7) 24 V IOH e b 400 mA VOH1 Output High Voltage (All Other Outputs) 24 V IOH e b 50 mA IIL Input Leakage Current (T0 T1 RD WR CS A0 EA) g 10 mA VSS s VIN s VCC IOZ Output Leakage Current (D0 –D7 High Z State) VSS a 0 45 g 10 mA s VIN s VCC ILI Low Input Load Current (P10P17 P20P27) 05 mA VIL e 0 8V ILI1 Low Input Load Current (RESET SS) 02 mA VIL e 0 8V IDD VDD Supply Current 15 mA Typical e 5 mA ICC a IDD Total Supply Current 125 mA Typical e 60 mA A C CHARACTERISTICS TA e 0 C to a 70 C VSS e 0V VCC e VDD e a 5V g 10% DBB READ Symbol Parameter Min Max Unit Test Conditions tAR CS A0 Setup to RD v 0 ns tRA CS A0 Hold after RD u 0 ns tRR RD Pulse Width 250 ns tAD CS A0 to Data Out Delay 225 ns CL e 150 pF tRD RDv to Data Out Delay 225 ns CL e 150 pF tDF RDu to Data Float Delay 100 ns tCY Cycle Time (except 8741A-8) 25 15 ms 6 0 MHz XTAL tCY Cycle Time (8741A-8) 4 17 15 ms 3 6 MHz XTAL 6 6 8741A DBB WRITE Symbol Parameter Min Max Units Test Conditions tAW CS A0 Setup to WR v 0 ns tWA CS A0 Hold after WRu 0 ns tWW WR Pulse Width 250 ns tDW Data Setup to WR u 150 ns tWD Data Hold after WRu 0 ns A C TIMING SPECIFICATION FOR PROGRAMMING TA e 0 C to a 70 C VCC e a 5V g 10% Symbol Parameter Min Max Units Test Conditions tAW Address Setup Time to RESET u 4tCY tWA Address Hold Time after RESETu 4tCY tDW Data in Setup Time to PROGu 4tCY tWD Data in Hold Time after PROGv 4tCY tPH RESET Hold Time to Verify 4tCY tVDDW VDD Setup Time to PROG u 4tCY tVDDH VDD Hold Time after PROG v 0 tPW Program Pulse Width 50 60 ms tTW Test 0 Setup Time for Program Mode 4tCY tWT Test 0 Hold Time after Program Mode 4tCY tDO Test 0 to Data Out Delay 4tCY tWW RESET Pulse Width to Latch Address 4tCY tr tf VDD and PROG Rise and Fall Times 05 20 ms tCY CPU Operation Cycle Time 50 ms tRE RESET Setup Time before EA u 4tCY NOTE 1 If TEST 0 is high tDO can be triggered by RESETu D C SPECIFICATION FOR PROGRAMMING TA e 25 C g 5 C VCC e 5V g 5% VDD e 25V g 1V Symbol Parameter Min Max Units Test Conditions VDOH VDD Program Voltage High Level 24 0 26 0 V VDDL VDD Voltage Low Level 4 75 5 25 V VPH PROG Program Voltage High Level 21 5 24 5 V VPL PROG Voltage Low Level 02 V VEAH EA Program or Verify Voltage High Level 21 5 24 5 V VEAL EA Voltage Low Level 5 25 V IDD VDD High Voltage Supply Current 30 0 mA IPROG PROG High Voltage Supply Current 16 0 mA IEA EA High Voltage Supply Current 10 mA 7 7 8741A A C CHARACTERISTICS DMA Symbol Parameter Min Max Units Test Conditions tACC DACK to WR or RD 0 ns tCAC RD or WR to DACK 0 ns tACD DACK to Data Valid 225 ns CL e 150 pF tCRQ RD or WR to DRQ Cleared 200 ns A C CHARACTERISTICS PORT 2 TA e 0 C to a 70 C VCC e a 5V g 10% Symbol Parameter Min Max Units Test Conditions tCP Port Control Setup before Falling Edge of PROG 10 ns tPC Port Control Hold after Falling Edge of PROG 100 ns tPR PROG to Time P2 Input Must Be Valid 810 ns tPF Input Data Hold Time 0 150 ns tDP Output Data Setup Time 250 ns tPD Output Data Hold Time 65 ns tPP PROG Pulse Width 1200 ns A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT 290241 – 23 290241 – 15 TYPICAL 8741A CURRENT CRYSTAL OSCILLATOR MODE 290241 – 11 Crystal series resistance should be k 75X at 6 MHz k 180X at 3 6 MHz 290241 – 14 8 8 8741A DRIVING FROM EXTERNAL SOURCE 290241 – 12 Both XTAL1 and XTAL2 should be driven Resistors to VCC are needed to ensure VIH e 3 8V if TTL circuitry is used LC OSCILLATOR MODE L C NOMINAL f 1 45 mH 20 pF 5 2 MHz fe 2q0LC 120 mH 20 pF 3 2 MHz C a 3Cpp C e 2 Cpp j 5– 10 pF Pin-to-Pin Capacitance 290241 – 13 Each C should be approximately 20 pF including stray capacitance WAVEFORMS READ OPERATION DATA BUS BUFFER REGISTER 290241 – 16 9 9 8741A WAVEFORMS WRITE OPERATION DATA BUS BUFFER REGISTER 290241 – 17 COMBINATION PROGRAM VERIFY MODE 290241 – 20 10 10 8741A WAVEFORMS VERIFY MODE 290241 – 21 NOTES 1 PROG must float if EA is low (i e i 23V) or if T0 e 5V for the 8741A 2 XTAL1 and XTAL2 driven by 3 6 MHz clock will give 7 17 ms tCY This is acceptable for 8741-8 parts as well as standard parts PROG must float or e 5V when EA is high 3 A0 must be held low (i e e 0V) during program verify modes DMA 290241 – 22 11 11 8741A PORT 2 TIMING 290241 – 19 PORT TIMING DURING EXTERNAL ACCESS (EA) 290241 – 18 On the rising edge of SYNC and EA is enabled port data is valid and can be strobed On the trailing edge of sync the program counter contents are available 12 12