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Source PDF: /mnt/main/jmc-storage/docs/Hardware/Intel/8742 UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER.pdf Like all conversions the text below should be fully readable as UTF-8 unicode text. --------------------------------------------------------------- 8742 UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER Y 8742 12 MHz Y DMA Interrupt or Polled Operation Y Pin Software and Architecturally Supported Compatible with 8741A Y Fully Compatible with all Intel and Most Y 8-Bit CPU plus ROM RAM I O Timer Other Microprocessor Families and Clock in a Single Package Y Expandable I O Y 2048 x 8 EPROM 128 x 8 RAM 8-Bit Y RAM Power-Down Capability Timer Counter 18 Programmable I O Y Over 90 Instructions 70% Single Byte Pins Y Available in EXPRESS Y One 8-Bit Status and Two Data Standard Temperature Range Registers for Asynchronous Slave-to- Master Interface The Intel 8742 is a general-purpose Universal Peripheral Interface that allows designers to grow their own customized solution for peripheral device control It contains a low-cost microcomputer with 2K of program memory 128 bytes of data memory 8-bit timer counter and clock generator in a single 40-pin package Interface registers are included to enable the UPI device to function as a peripheral controller in the MCS -48 MCS-51 MCS-80 MCS-85 8088 8086 and other 8- 16-bit systems The 8742 is software pin and architecturally compatible with the 8741A The 8742 doubles the on-chip memory space to allow for additional features and performance to be incorporated in upgraded 8741A de- signs For new designs the additional memory and performance of the 8742 extends the UPI concept to more complex motor control tasks 80-column printers and process control applications as examples 290256 – 2 Figure 1 Pin Configuration November 1991 Order Number 290256-001 1 8742 290256 – 1 Figure 2 Block Diagram 2 2 8742 Table 1 Pin Description DIP Symbol Pin Type Name and Function No TEST 0 1 I TEST INPUTS Input pins which can be directly tested using conditional branch TEST 1 39 instructions FREQUENCY REFERENCE TEST 1 (T1) also functions as the event timer input (under software control) TEST 0 (T0) is used during PROM programming and EPROM verification XTAL 1 2 I INPUTS Inputs for a crystal LC or an external timing signal to determine the internal XTAL 2 3 oscillator frequency RESET 4 I RESET Input used to reset status flip-flops and to set the program counter to zero RESET is also used during EPROM programming and verification SS 5 I SINGLE STEP Single step input used in conjunction with the SYNC output to step the program through each instruction (EPROM) This should be tied to a 5V when not used CS 6 I CHIP SELECT Chip select input used to select one UPI microcomputer out of several connected to a common data bus EA 7 I EXTERNAL ACCESS External access input which allows emulation testing and EPROM verification This pin should be tied low if unused RD 8 I READ I O read input which enables the master CPU to read data and status words from the OUTPUT DATA BUS BUFFER or status register A0 9 I COMMAND DATA SELECT Address Input used by the master processor to indicate whether byte transfer is data (A0 e 0 F1 is reset) or command (A0 e 1 F1 is set) A0 e 0 during program and verify operations WR 10 I WRITE I O write input which enables the master CPU to write data and command words to the UPI INPUT DATA BUS BUFFER SYNC 11 O OUTPUT CLOCK Output signal which occurs once per UPI instruction cycle SYNC can be used as a strobe for external circuitry it is also used to synchronize single step operation D0 – D7 12–19 I O DATA BUS Three-state bidirectional DATA BUS BUFFER lines used to interface the UPI (BUS) microcomputer to an 8-bit master system data bus P10 – P17 27–34 I O PORT 1 8-bit PORT 1 quasi-bidirectional I O lines P20 – P27 21–24 I O PORT 2 8-bit PORT 2 quasi-bidirectional I O lines The lower 4 bits (P20 –P23) interface 35– 38 directly to the 8243 I O expander device and contain address and data information during PORT 4–7 access The upper 4 bits (P24 –P27) can be programmed to provide interrupt Request and DMA Handshake capability Software control can configure P24 as Output Buffer Full (OBF) interrupt P25 as Input Buffer Full (IBF) interrupt P26 as DMA Request (DRQ) and P27 as DMA ACKnowledge (DACK) PROG 25 I O PROGRAM Multifunction pin used as the program pulse input during PROM programming During I O expander access the PROG pin acts as an address data strobe to the 8243 This pin should be tied high if unused VCC 40 POWER a 5V main power supply pin VDD 26 POWER a 5V during normal operation a 21V during programming operation Low power standby supply pin VSS 20 GROUND Circuit ground potential 3 3 8742 UPI-42 FEATURES the IBF Status Bit A ‘‘0’’ written to P25 disables the IBF pin (the pin remains low) This pin can be 1 Two Data Bus Buffers one for input and one for used to indicate that the UPI is ready for data output This allows a much cleaner Master Slave protocol 290256 – 5 Data Bus Buffer Interrupt Capability 290256 –3 EN FLAGS Op Code 0F5H 2 8 Bits of Status 1 1 1 1 0 1 0 1 ST7 ST6 ST5 ST4 F1 F0 IBF OBF D7 D0 5 P26 and P27 are port pins or DMA handshake pins D7 D6 D5 D4 D3 D2 D1 D0 for use with a DMA controller These pins default ST4 –ST7 are user definable status bits These to port pins on Reset bits are defined by the ‘‘MOV STS A’’ single byte If the ‘‘EN DMA’’ instruction has been executed single cycle instruction Bits 4–7 of the acccumu- P26 becomes the DRQ (DMA Request) pin A ‘‘1’’ lator are moved to bits 4–7 of the status register written to P26 causes a DMA request (DRQ is acti- Bits 0–3 of the status register are not affected vated) DRQ is deactivated by DACK # RD MOV STS A Op Code 90H DACK # WR or execution of the ‘‘EN DMA’’ in- 1 0 0 1 0 0 0 0 struction D7 D0 If ‘‘EN DMA’’ has been executed P27 becomes the DACK (DMA Acknowledge) pin This pin acts 3 RD and WR are edge triggered IBF OBF F1 and as a chip select input for the Data Bus Buffer reg- INT change internally after the trailing edge of RD isters during DMA transfers or WR 290256 –4 During the time that the host CPU is reading the 290256 – 6 status register the 8742 is prevented from updat- ing this register or is ‘‘locked out’’ DMA Handshake Capability 4 P24 and P25 are port pins or Buffer Flag pins EN DMA Op Code 0E5H which can be used to interrupt a master proces- sor These pins default to port pins on Reset 1 1 1 0 0 1 0 1 If the ‘‘EN FLAGS’’ instruction has been execut- D7 D0 ed P24 becomes the OBF (Output Buffer Full) pin 6 The RESET input on the 8742 includes a 2-stage A ‘‘1’’ written to P24 enables the OBF pin (the pin outputs the OBF Status Bit) A ‘‘0’’ written to P24 synchronizer to support reliable reset operation for 12 MHz operation disables the OBF pin (the pin remains low) This pin can be used to indicate that valid data is avail- 7 When EA is enabled on the 8742 the program able from the UPI-41A (in Output Data Bus Buff- counter is placed on Port 1 and the lower three er) bits of Port 2 (MSB e P22 LSB e P10) On the If ‘‘EN FLAGS’’ has been executed P25 becomes 8742 this information is multiplexed with PORT the IBF (Input Buffer Full) pin A ‘‘1’’ written to P25 DATA (see port timing diagrams at end of this data sheet) enables the IBF pin (the pin outputs the inverse of 4 4 8742 APPLICATIONS 290256 – 8 290256 –7 Figure 4 8048H-8742 Interface Figure 3 8088-8742 Interface 290256 –9 290256 – 10 Figure 5 8742-8243 Keyboard Scanner Figure 6 8742 80-Column Matrix Printer Interface 5 5 8742 PROGRAMMING VERIFYING AND 7 Data applied to BUS ERASING THE 8742 EPROM 8 VDD e 21V (programming power) 9 PROG e VCC followed by one 50 ms pulse to Programming Verification 18V In brief the programming process consists of acti- 10 VDD e 5V vating the program mode applying an address 11 TEST 0 e 5V (verify mode) latching the address applying data and applying a 12 Read and verify data on BUS programming pulse Each word is programmed com- 13 TEST 0 e 0V pletely before moving on to the next and is followed by a verification step The following is a list of the 14 RESET e 0V and repeat from step 5 pins used for programming and a description of their 15 Programmer should be at conditions of step 1 functions when 8742 is removed from socket Pin Function XTAL 1 Clock-Input 8742 Erasure Characteristics Reset Initialization and Address Latching The erasure characteristics of the 8742 are such Test 0 Selection of Program or Verify Mode that erasure begins to occur when exposed to light EA Activation of Program Verify Modes with wavelengths shorter than approximately 4000 BUS Address and Data Input Angstroms ( ) It should be noted that sunlight and Data Output During Verify certain types of fluorescent lamps have wavelengths P20–12 Address Input in the 3000-4000 range Data shows that constant VDD Programming Power Supply exposure to room level fluorescent lighting could erase the typical 8742 in approximately 3 years PROG Program Pulse Input while it would take approximately one week to cause WARNING An attempt to program a missocketed 8742 will result in severe dam- erasure when exposed to direct sunlight If the 8742 age to the part An indication of a properly socketed part is the ap- is to be exposed to these types of lighting conditions pearance of the SYNC clock output The lack of this clock may be for extended periods of time opaque labels are used to disable the programmer available from Intel which should be placed over the 8742 window to prevent unintentional erasure The Program Verify sequence is 1 A0 e 0V CS e 5V EA e 5V RESET e 0V The recommended erasure procedure for the 8742 TESTO e 5V VDD e 5V clock applied or inter- is exposure to shortwave ultraviolet light which has a nal oscillator operating BUS floating PROG e wavelength of 2537 The integrated dose (i e UV 5V intensity c exposure time) for erasure should be a 2 Insert 8742 in programming socket minimum of 15 w-sec cm2 The erasure time with this dosage is approximately 15 to 20 minutes using 3 TEST 0 e 0V (select program mode) an ultraviolet lamp with a 12 000 mW cm2 power rat- 4 EA e 18V (active program mode) ing The 8742 should be placed within one inch of 5 Address applied to BUS and P20–22 the lamp tubes during erasure Some lamps have a filter on their tubes which should be removed before 6 RESET e 5V (latch address) erasure 6 6 8742 ABSOLUTE MAXIMUM RATINGS NOTICE This is a production data sheet The specifi- cations are subject to change without notice Ambient Temperature Under Bias 0 C to 70 C WARNING Stressing the device beyond the ‘‘Absolute Storage Temperature b 65 C to a 150 C Maximum Ratings’’ may cause permanent damage Voltage on Any Pin With Respect These are stress ratings only Operation beyond the to Ground b 0 5 to a 7V ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ Power Dissipation 1 5W may affect device reliability D C CHARACTERISTICS TA e 0 to a 70 C VCC e VDD e a 5V g 10% 8742 Test Symbol Parameter Units Conditions Min Max VIL Input Low Voltage (Except XTAL1 XTAL2 RESET) b0 5 08 V VIL1 Input Low Voltage (XTAL1 XTAL2 RESET) b0 5 06 V VIH Input High Voltage (Except XTAL1 XTAL2 RESET) 20 VCC V VIH1 Input High Voltage (XTLA1 XTAL2 RESET) 35 VCC V VOL Output Low Voltage (D0 –D7) 0 45 V IOL e 2 0 mA VOL1 Output Low Voltage (P10 –P17 P20 –P27 Sync) 0 45 V IOL e 1 6 mA VOL2 Output Low Voltage (PROG) 0 45 V IOL e 1 0 mA VOH Output High Voltage (D0 –D7) 24 V IOH e b 400 mA VOH1 Output High Voltage (All Other Outupts) 24 IOH e b 50 mA IIL Input Leakage Current (T0 T1 RD WR CS A0 EA) g 10 mA VSS s VIN s VCC IOFL Output Leakage Current (D0 –D7 High Z State) VSS a 0 45 g 10 mA s VOUT s VCC ILI Low Input Load Current (P10 –P17 P20 –P27) 03 mA VIL e 0 8V ILI1 Low Input Load Current (RESET SS) 02 mA VIL e 0 8V IDD VDD Supply Current 10 mA Typical e 5 mA ICC a IDD Total Supply Current 125 mA Typical e 60 mA IIH Input Leakage Current (P10 –P17 P20 –P27) 100 mA VIN e VCC CIN Input Capacitance 10 pF C1 0 I O Capacitance 20 pF D C CHARACTERISTICS PROGRAMMING TA e 25 C g 5 C VCC e 5V g 5% VDD e 21V g 0 5V Symbol Parameter Min Max Units Test Conditions VDOH VDD Program Voltage High Level 20 5 21 5 V VDDL VDD Voltage Low Level 4 75 5 25 V VPH PROG Program Voltage High Level 17 5 18 5 V VPL PROG Voltage Low Level VCC b 0 5 VCC V VEAH EA Program or Verify Voltage High Level 17 5 18 5 V VEAL EA Voltage Low Level 5 25 V IDD VDD High Voltage Supply Current 30 0 mA IPROG PROG High Voltage Supply Current 10 mA IEA EA High Voltage Supply Current 10 mA 7 7 8742 A C CHARACTERISTICS TA e 0 C to a 70 C VSS e 0V VCC e VDD e a 5V g 10% DBB READ 8742 Symbol Parameter Units Min Max tAR CS A0 Setup to RDv 0 ns tRA CS A0 Hold after RDu 0 ns tRR RD Pulse Width 160 ns tAD CS A0 to Data Out Delay 130 ns tRD RDv to Data Out Delay 130 ns tDF RDu to Data Float Delay 85 ns tCY Cycle Time 1 25 15 ms(1) DBB WRITE Symbol Parameter Min Max Units tAW CS A0 Setup to WRv 0 ns tWA CS A0 Hold after WRu 0 ns tWW WR Pulse Width 160 ns tDW Data Setup to WRu 130 ns tWD Data Hold after WRu 0 ns NOTE 1 TCY e 15 f(XTAL) A C CHARACTERISTICS TA e 25 C g 5 C VCC e 5V g 5% VDD e a 21V g 0 5 PROGRAMMING Symbol Parameter Min Max Units Test Conditions tAW Address Setup Time to RESETu 4tCY tWA Address Hold Time after RESETu 4tCY tDW Data in Setup Time to PROGu 4tCY tWD Data in Hold Time after PROGv 4tCY tPH RESET Hold Time to Verify 4tCY tVDDW VDD Setup Time to PROGu 0 10 mS tVDDH VDD Hold Time after PROGu 0 10 mS tPW Program Pulse Width 50 60 mS tTW Test 0 Setup Time for Program Mode 4tCY tWT Test 0 Hold Time after Program Mode 4tCY tDO Test 0 to Data Out Delay 4tCY tWW RESET Pulse Width to Latch Address 4tCY tr t f VDD and PROG Rise and Fall Times 05 20 ms tCY CPU Operation Cycle Time 40 ms tRE RESET Setup Time before EAu 4tCY NOTE If TEST 0 is high tDO can be triggered by RESETu 8 8 8742 A C CHARACTERISTICS DMA 8642 8742 Symbol Parameter Units Min Max tACC DACK to WR or RD 0 ns tCAC RD or WR to DACK 0 ns tACD DACK to Data Valid 130 ns tCRQ RD or WR to DRQ Cleared 100 ns(1) NOTE 1 CL e 150 pF A C CHARACTERISTICS PORT 2 TA e 0 C to a 70 C VCC e a 5V g 10% 8742 8642(3) Symbol Parameter f(tCY) Units Min Max tCP Port Control Setup before Falling Edge of PROG 1 15 tCY b 28 55 ns(1) tPC Port Control Hold after Falling Edge of PROG 1 10 tCY 125 ns(2) tPR PROG to Time P2 Input Must Be Valid 8 15 tCY b 16 650 ns(1) tPF Input Data Hold Time 0 150 ns(2) tDP Output Data Setup Time 2 10 tCY 250 ns(1) tPD Output Data Hold Time 1 10 tCY b 80 45 ns(2) tPP PROG Pulse Width 6 10 tCY 750 ns NOTES 1 CL e 80 pF 2 CL e 20 pF 3 tCY e 1 25 ms A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT INPUT OUTPUT 290256 – 12 290256 – 11 CRYSTAL OSCILLATOR MODE DRIVING FROM EXTERNAL SOURCE 290256 – 13 Crystal Series Resistance Should be k750 at 12 MHz k 180X at 3 6 MHz 290256 – 14 Rise and Fall Times Should Not Exceed 20 ns Resis- tors to VCC are Needed to Ensure VIH e 3 5V if TTL Circuitry is Used 9 9 8742 LC OSCILLATOR MODE 1 fe 2q0LC L C NOMINAL C a 3Cpp 45 H 20 pF 5 2 MHz C e 120 H 20 pF 3 2 MHz 2 Cpp j 5 pF– 10 pF Pin-to-Pin Capacitance 290256 – 15 Each C Should be Approximately 20 pF including Stray Capacitance WAVEFORMS READ OPERATION DATA BUS BUFFER REGISTER 290256 – 16 WRITE OPERATION DATA BUS BUFFER REGISTER 290256 – 17 CLOCK TIMING 290256 – 23 10 10 8742 WAVEFORMS COMBINATION PROGRAM VERIFY MODE 290256 – 18 VERIFY MODE 290256 – 19 NOTES 1 PROG must float if EA is low or EA is low or if TEST0 e 5V 2 A0 must be held low (i e e 0V) during program verify modes 3 Test 0 must be held high The 8742 EPROM can be programmed by the fol- 2 iUP-200 iUP-201 PROM Programmer with the lowing Intel products iUP-F87 44 Personality Module 1 Universal PROM Programmer (UPP 103) periph- eral of the Intellec Development System with a UPP-549 Personality Card 11 11 8742 WAVEFORMS (Continued) DMA 290256 – 20 PORT 2 290256 – 21 PORT TIMING DURING EXTERNAL ACCESS (EA) 290256 – 22 On the Rising Edge of SYNC and EA is Enabled Port Data is Valid and can be Strobed on the Trailing Edge of Sync the Program Counter Contents are Available 12 12