This file is raw output from pdftotext and may not be ideal for distribution. If you are a maintainer for Hackipedia, please sit down when you have time and clean this text version up. Source PDF: /mnt/fw-js/docs/Hardware/Integrated Circuit Systems/ICS90C64A - Dual Video-Memory Clock Generator (WD90C11 compat).pdf Like all conversions the text below should be fully readable as UTF-8 unicode text. --------------------------------------------------------------- Integrated ICS90C64A Circuit Systems, Inc. Dual Video/Memory Clock Generator Introduction Features The Integrated Circuit Systems ICS90C64A is a dual clock • Improved compatibility with Western Digital Controllers generator for VGA applications. It simultaneously generates • 100% backward compatible with ICS90C63 and ICS90C64 two clocks. One clock is for the video memory, and the other • Dual Clock generator for the IBM compatible Western is the video dot clock. Digital Imaging Video Graphics Array (VGA) LSI devices, and 8514/A chip sets This data sheet supplies sales order information, a functional • Integral loop filter components. Reduce cost and phase-jitter overview, signal pin details, a block diagram, AC/DC char- • Generates 15 video clock frequencies (including 25.175 acteristics, timing diagrams, and package mechanical infor- and 28.322 MHz) derived from a 14.318 MHz system clock mation. reference frequency • On-chip generation of eight memory clock frequencies. • Video clock is selectable among the fifteen internally gen- erated clocks and one external clock • CMOS technology Description • Available in 20-pin PLCC, SOIC, and DIP packages The Integrated Circuit Systems Video Graphics Array Clock Generator (ICS90C64A) is capable of producing different output frequencies under firmware control. The video output frequency is derived from a 14.318 MHz system clock avail- able in IBM PC/XT/AT and Personal System/2 computers. It is designed to work with Western Digital Imaging Video Graphics Array and 8514/A devices to optimize video subsys- tem performance. The video dot clock output may be one of fifteen internally- generated frequencies or one external input. The selection of the video dot clock frequency is done through four inputs. • VSEL0 • VSEL1 • VSEL2 • VSEL3 VSEL0 and VSEL1 are latched by the SELEN signal. VSEL2 and VSEL3 are used as direct inputs to the VCLK selection. Table 1-1 is the truth table for VCLK selection. The input and truth table have been designed to allow a direct connection to one of the many Western Digital Imaging VGA controllers or 8514/A chip sets. The MCLK output is one of eight internally-generated frequen- cies as shown in Table 1-2. The various VCLK and MCLK frequencies are derived from the 14.318 MHz Input frequency. Note: ICS90C64AN (DIP) pin-out is identical to ICS90C64AM (SOIC) pin-out. 90C64ARevA111095 ICS90C64A ICS90C64A VGA Interface The ICS90C64A has two system interfaces: System Bus and normally have a status bit that indicates to the VGA controller VGA Controller, as well as analog filters and seven user that it is working with a clock chip. When working with a clock programmable inputs. Figure 2-1 shows how the Integrated chip the VGA controller changes two of its clock inputs, Circuit Systems VGA Clock ICS90C64A is connected to a VCLK1 and VCLK2, to outputs. These outputs are used to VGA controller. Western Digital Imaging VGA controllers select the required video frequency. Figure 2-1 ICS90C64A Interface Note: C2 should be placed as close as possible to the ICS90C64A AVDD pin. 2 ICS90C64A System Bus Inputs Analog Filters The system bus inputs are: The analog filters are integral to the ICS90C64A device. No external components are required. This feature reduces PC • CLK1 board space requirements and component costs. Phase-jitter is • VSEL0 reduced as externally-generated noise cannot easily influence • VSEL1 the phase-locked loop filter. The ICS90C64A uses the system bus 14.318 MHz clock as a reference to generate all its frequencies for both video and User-Definable Inputs memory clocks. Data lines D2 and D3 are commonly used as inputs to VSEL0 and VSEL1 for video frequency selection. The user-definable inputs are: • EXTCLK • VLCKE, MCLKE • MSELO-2 Inputs from VGA Controller • VSEL2, VSEL3 The VGA controller input to the ICS90C64A is: EXTCLK is an additional input that may be internally routed • SELEN to the VCLK output. This additional input is useful for sup- porting modes that require frequencies not provided by the The ICS90C64A is programmed to generate different video ICS90C64A. clock frequencies using the inputs of VSEL0, VSEL1, VSEL2, and VSEL3. The signals VSEL2 and VSEL3 may be supplied VCLKE and MCLKE are the output enable signals for VCLK by the VGA controller as is the case in Western Digital Imaging and MCLK. When low, the respective output is tristated. VGA controllers. The inputs VSEL0-1 are latched with the signal SELEN. The SELEN input should be an active low MSEL0-2 are the memory clock (MCLK) select lines. pulse. This active low pulse is generated in Western Digital Table 1-2 shows how MCLK frequencies are selected. All Imaging VGA controllers during I/O writes to internal register signals in this group have internal pull-up resistors. 3C2h. VSEL2 and VSEL3 are video clock (VCLK) select lines that Note: Only VSEL0 and VSEL1 are latched with signal SE- can select additional VCLK frequencies. See Table 1-1. LEN. VSEL2 and VSEL3 have internal pull-ups. Outputs to VGA Controller The outputs from the ICS90C64A to the VGA controller are: • MCLK • VCLK MCLK and VCLK are the two clock outputs to the VGA controller. 3 ICS90C64A Power Considerations The ICS90C64A product requires an AVDD supply free of fast rise time transients. This requirement may be met in several ways and is highly dependent on the characteristics of the host system. A VGA adapter card is unique in that it must function in an unknown environment. +5 volt power quality is depend- ent not only on the quality of the power supply resident in the host system, but also on the other cards plugged into the host’s backplane. Power supply noise ranges from fair to terrible. As the VGA adapter manufacturer has no control over this, he must assume the worst. The best solution is to create a clean +5 volts by deriving it from the +12 volt supply by using a zener diode and dropping resistor. A 470 Ohm resistor and 5.1 volt Zener diode are the least costly way to accomplish this. A .047 to .1 microfarad bypass capacitor tied from AVDD to AVss insures good high-frequency decoupling of this point. Laptop and notebook computers have entirely different prob- lems with power. Typically they have no +12 volt supply; however, they are much quieter electrically. Because the de- signer has complete control of the system architecture, he can place sensitive components and systems such as the RAMDAC and Dual Video/Memory Clock away from DRAM and other noise-generating components. Most systems provide power that is clean enough to allow for jitter- free Dual Video/Mem- ory Clock performance if the +5 volt supply is decoupled with a resistor and 22 microfarad Tantalum capacitor. Digital inputs that are desired to be held at a static logical high level should not be tied to +5 volts as this will result in excessive current drain through the ESD protection diode. The internal pull-up resistors will adequately keep these inputs high. 4 ICS90C64A Table 1-1 VCLK Selection VCLK Frequency (MHz) 3 2 1 0 ICS90C64A ICS90C64A-903 ICS90C64A-907 ICS90C64A-909 0 0 0 0 30.0 30.0 30.250 30.0 0 0 0 1 77.25 77.25 77.25 77.25 0 0 1 0 EXTCLK EXTCLK EXTCLK EXTCLK 0 0 1 1 80.0 80.0 80.0 80.0 0 1 0 0 31.5 31.5 31.5 31.5 0 1 0 1 36.0 36.0 35.5 36.0 0 1 1 0 75.0 75.0 75.0 75.0 0 1 1 1 50.0 50.0 72.0 50.0 1 0 0 0 40.0 40.0 40.0 40.0 1 0 0 1 50.0 50.0 50.0 50.0 1 0 1 0 32.0 32.0 32.0 32.0 1 0 1 1 44.9 44.9 44.9 44.9 1 1 0 0 25.175 25.175 25.175 25.175 1 1 0 1 28.322 28.322 28.322 28.322 1 1 1 0 65.0 65.0 65.0 65.0 1 1 1 1 36.0 36.0 36.0 36.0 Table 1-2 MCLK Selection MCLK Frequencies (MHz) 2 1 0 ICS90C64A ICS90C64A-903 ICS90C64A-907 ICS90C64A-909 0 0 0 33.0 33.0 65.0 75.0 0 0 1 49.218 49.218 49.218 40.0 0 1 0 60.0 60.0 60.0 45.0 0 1 1 30.5 30.5 62.5 50.0 1 0 0 41.612 41.612 41.612 55.0 1 0 1 37.5 37.5 37.5 60.0 1 1 0 36.0 36.0 55.0 65.0 1 1 1 44.296 44.296 44.296 70.0 5 ICS90C64A Figure 2-2 ICS90C64A Functional Block Diagram 6 ICS90C64A Pin Descriptions The following table provides the pin descriptions for the 20-pin ICS90C64A packages. PIN PIN NUMBER SYMBOL TYPE DESCRIPTION 1 CLK1 IN Reference input clock from system. 2 MSEL2 IN Select input for MCLK selection. 3 EXTCLK IN External clock input for an additional frequency. 4 VSEL1 IN Control input for VCLK selection. 5 VSEL0 IN Control input for VCLK selection. 6 SELEN IN Strobe for latching VSEL(0,1) (low enable). 7 VSEL2 IN Control input for VCLK selection. 8 VSEL3 IN Control input for VCLK selection. 9 MSEL0 IN Select input for MCLK selection. 10 DGND - Ground for Digital Circuit. 11 MSEL1 IN Select input for MCLK selection. 12 MCLK OUT Memory Clock Output. 13 NC - No connection. 14 MCLKE IN Enable input for MCLK output (high enables output). 15 AVDD - Power supply for analog circuit. 16 AGND - Ground for analog circuit. 17 NC - No connection. 18 VCLKE IN Enable input for VCLK output (high enables output). 19 VCLK OUT Video Clock Output. 20 DVDD - Power supply for Digital Circuit. Note: CLK1, EXTCLK,VSEL0, VSEL1,VSEL2, VSEL3, SELEN, MSEL0, MSEL1, MSEL2, VCLKE, and MCLKE - input pins have internal pull-up resistors. 7 ICS90C64A Absolute Maximum Ratings Standard Test Conditions Ambient Temperature 0°C to 70°C The characteristics below apply for the following standard test under bias conditions, unless otherwise noted. All voltages are referenced to VSS (OV Ground). Positive current flows into the referenced Storage temperature -40°C to 125 °C pin. Voltage on all inputs 0.5 to 7 volts and outputs with Operating Temperature 0°C to 70°C respect to VSS range Power supply voltage 4.75 to 5.25 volts Note: Stresses above those listed under Absolute Maximum Rating may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of the specifications is not implied. Exposure to abso- lute maximum rating conditions for extended periods may affect product reliability. DC Characteristics SYMBOL PARAMETER MIN TYP MAX UNITS CONDITIONS VIL Input Low Voltage VSS 0.8 V VIH Input High Voltage 2.0 VDD V IIH Input Leakage Current - 10 µA Vin = VDD VOL Output Low Voltage - 0.4 V IOL = 8.0 mA VOH Output High Voltage VDD-.4 - IOH = 4.0mA VOH Output High Voltage 2.4 - V IOH = 8.0 mA ICC Supply Current - 20 28 mA No load VCLK = 28 MHz MCLK = 40 MHz ICC Supply Current - 27 35 mA No load VCLK = 80 MHz MCLK = 40 MHz RUP Internal Pull-up Resistors 50 - K ohms VDD = 5V Cin Input Pin Capacitance - 8 pF FC = 1 MHz Cout Output Pin Capacitance - 12 pF FC = 1 MHz 8 ICS90C64A AC Timing Characteristics The following notes apply to all of the parameters presented in this section: 1. REFCLK = 14.318 MHz 2. TC = 1/FC 3. All units are in nanoseconds (ns), unless labeled otherwise. 4. Output pin loading = 15pF SYMBOL PARAMETER MIN TYP MAX NOTES SELEN TIMING Tpwen Enable Pulse Width 20 Tsuen Setup Time Data to Enable 20 Thden Hold Time Data to Enable 10 Reference Input Clock Tr Rise Time 10 Phase-Jitter 1 ns max. Tf Fall Time 10 Duty Cycle 42.5% min. to 57.5% max. MCLK and VCLK TIMINGS Tr Rise Time .9 1.5 .8V-2.0V* Tf Fall Time .9 1.5 2.0V-.8V Tr Rise Time 1.2 2.0 .3 VDD-.7 VDD Tf Fall Time 1.2 2.0 .7 VDD-.3 VDD Thigh Duty Cycle 50% 60% 1.4V Switch Point Thigh Duty Cycle 45% 55% VDD/2 Switch Point Frequency Error 0.5 % Maximum Frequency 135 MHz Propagation Delay for 20 ns Pass Through Frequency Output Enable to Tri-State 15 ns (into and out of) time *WD90C11 Video Controller is designed with TTL level input thresholds on the inputs driven by the ICS90C64A VCLK and MCLK outputs. The later controllers (WD90C20, WD90C22, WD90C26, WD90C30, and WD90C31) are designed with input switch points of VCC/2 (CMOS). 9 ICS90C64A Figure 5-1 ICS90C64A Timing 10 ICS90C64A 20-Pin DIP Package 20-Pin SOIC Package Note: PLCC Package All Package Dimensions in inches. Ordering Information ICS90C64AN or ICS90C64AM or ICS90C64AV Example: ICS XXXX- XXX N Package Type N=DIP (Plastic) V=PLCC M=SOIC Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3-6 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device 11