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Source PDF: /mnt/fw-js/docs/Disassembly and analysis/documentation - Components of Pinnacle MovieBox USB/LC547A/scas301r.pdf Like all conversions the text below should be fully readable as UTF-8 unicode text. --------------------------------------------------------------- SN54LVC574A, SN74LVC574A OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 D Operate From 1.65 V to 3.6 V D Support Mixed-Mode Signal Operation on D Inputs Accept Voltages to 5.5 V All Ports (5-V Input/Output Voltage With 3.3-V VCC) D Specified From −40°C to 85°C, −40°C to 125°C, and −55°C to 125°C D Ioff Supports Partial-Power-Down Mode Operation D Max tpd of 7 ns at 3.3 V D Typical VOLP (Output Ground Bounce) D Latch-Up Performance Exceeds 250 mA Per JESD 17 <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) >2 V at VCC = 3.3 V, TA = 25°C − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SN54LVC574A . . . J OR W PACKAGE SN74LVC574A . . . RGY PACKAGE SN54LVC574A . . . FK PACKAGE SN74LVC574A . . . DB, DGV, DW, N, NS, (TOP VIEW) (TOP VIEW) OR PW PACKAGE VCC VCC OE 1Q 2D 1D OE (TOP VIEW) OE 1 20 VCC 1 20 3 2 1 20 19 3D 4 18 2Q 1D 2 19 1Q 1D 2 19 1Q 4D 5 17 3Q 2D 3 18 2Q 2D 3 18 2Q 5D 6 16 4Q 3D 4 17 3Q 3D 4 17 3Q 6D 7 15 5Q 4D 5 16 4Q 4D 5 16 4Q 7D 8 14 6Q 5D 6 15 5Q 5D 6 15 5Q 9 10 11 12 13 6D 7 14 6Q 6D 7 14 6Q 8D GND CLK 8Q 7Q 7D 8 13 7Q 7D 8 13 7Q 8D 9 12 8Q 8D 9 12 8Q GND 10 11 CLK 10 11 GND CLK description/ordering information The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2005, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL PRF 38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVC574A, SN74LVC574A OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING QFN − RGY Reel of 1000 SN74LVC574ARGYR LC574A −40 C 85°C −40°C to 85 C VFBGA − GQN SN74LVC574AGQNR Reel of 1000 LC574A VFBGA − ZQN (Pb-free) SN74LVC574AZQNR PDIP − N Tube of 20 SN74LVC574AN SN74LVC574AN Tube of 25 SN74LVC574ADW SOIC − DW LVC574A Reel of 2000 SN74LVC574ADWR SOP − NS Reel of 2000 SN74LVC574ANSR LVC574A −40 C 125°C −40°C to 125 C SSOP − DB Reel of 2000 SN74LVC574ADBR LC574A Tube of 70 SN74LVC574APW TSSOP − PW Reel of 2000 SN74LVC574APWR LC574A Reel of 250 SN74LVC574APWT TVSOP − DGV Reel of 2000 SN74LVC574ADGVR LC574A CDIP − J Tube of 20 SNJ54LVC574AJ SNJ54LVC574AJ −55 C 125°C −55°C to 125 C CFP − W Tube of 85 SNJ54LVC574AW SNJ54LVC574AW LCCC − FK Tube of 55 SNJ54LVC574AFK SNJ54LVC574AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. GQN OR ZQN PACKAGE (TOP VIEW) terminal assignments 1 2 3 4 1 2 3 4 A A 1D OE VCC 1Q B B 3D 3Q 2D 2Q C C 5D 4D 5Q 4Q D D 7D 7Q 6D 6Q E E GND 8D CLK 8Q FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D Q L ↑ H H L ↑ L L L L X Q0 H X X Z 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVC574A, SN74LVC574A OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 logic diagram (positive logic) 1 OE 11 CLK C1 19 1Q 2 1D 1D To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W (see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W (see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W (see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Power dissipation, Ptot (TA = −40°C to 125°C) (see Notes 5 and 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. 5. For the DW package: above 70°C the value of Ptot derates linearly with 8 mW/K. 6. For the DB, DGV, N, NS, and PW packages: above 60°C the value of Ptot derates linearly with 5.5 mW/K. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVC574A, SN74LVC574A OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 recommended operating conditions (see Note 7) SN54LVC574A −55 TO 125°C UNIT MIN MAX Operating 2 3.6 VCC Supply voltage V Data retention only 1.5 VIH High-level input voltage VCC = 2.7 V to 3.6 V 2 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V VI Input voltage 0 5.5 V High or low state 0 VCC VO Output voltage V 3−state 0 5.5 VCC = 2.7 V −12 IOH High-level output current mA VCC = 3 V −24 VCC = 2.7 V 12 IOL Low-level output current mA VCC = 3 V 24 ∆t/∆v Input transition rise or fall rate 6 ns/V NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. recommended operating conditions (see Note 7) SN74LVC574A TA = 25°C −40 TO 85°C −40 TO 125°C UNIT MIN MAX MIN MAX MIN MAX Operating 1.65 3.6 1.65 3.6 1.65 3.6 VCC Supply voltage V Data retention only 1.5 1.5 1.5 VCC = 1.65 V to 1.95 V 0.65 × VCC 0.65 × VCC 0.65 × VCC High-level input VIH VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 V voltage VCC = 2.7 V to 3.6 V 2 2 2 VCC = 1.65 V to 1.95 V 0.35 × VCC 0.35 × VCC 0.35 × VCC Low-level input VIL VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 V voltage VCC = 2.7 V to 3.6 V 0.8 0.8 0.8 VI Input voltage 0 5.5 0 5.5 0 5.5 V High or low state 0 VCC 0 VCC 0 VCC VO Output voltage V 3−state 0 5.5 0 5.5 0 5.5 VCC = 1.65 V −4 −4 −4 High-level VCC = 2.3 V −8 −8 −8 IOH mA output current VCC = 2.7 V −12 −12 −12 VCC = 3 V −24 −24 −24 VCC = 1.65 V 4 4 4 Low-level VCC = 2.3 V 8 8 8 IOL mA output current VCC = 2.7 V 12 12 12 VCC = 3 V 24 24 24 ∆t/∆v Input transition rise or fall rate 6 6 6 ns/V NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVC574A, SN74LVC574A OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LVC574A PARAMETER TEST CONDITIONS VCC −55 TO 125°C UNIT MIN TYP† MAX IOH = −100 µA 2.7 V to 3.6 V VCC − 0.2 2.7 V 2.2 VOH IOH = −12 mA V 3V 2.4 IOH = −24 mA 3V 2.2 IOL = 100 µA 2.7 V to 3.6 V 0.2 VOL IOL = 12 mA 2.7 V 0.4 V IOL = 24 mA 3V 0.55 II VI = 5.5 V or GND 3.6 V ±5 µA IOZ VO = 0 to 5.5 V 3.6 V ±15 µA VI = VCC or GND 10 ICC IO = 0 3.6 V µA A 3.6 V ≤ VI ≤ 5.5 V‡ 10 ∆ICC One input atVCC − 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 µA Ci VI = VCC or GND 3.3 V 4 pF Co VO = VCC or GND 3.3 V 5.5 pF † TA = 25°C ‡ This applies in the disabled state only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVC574A, SN74LVC574A OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN74LVC574A PARAMETER TEST CONDITIONS VCC TA = 25°C −40 TO 85°C −40 TO 125°C UNIT MIN TYP MAX MIN MAX MIN MAX IOH = −100 µA 1.65 V to 3.6 V VCC − 0.2 VCC − 0.2 VCC − 0.2 IOH = −4 mA 1.65 V 1.29 1.2 1.2 IOH = −8 mA 2.3 V 1.9 1.7 1.7 VOH V 2.7 V 2.2 2.2 2.2 IOH = −12 mA 3V 2.4 2.4 2.4 IOH = −24 mA 3V 2.3 2.2 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.1 0.2 0.2 IOL = 4 mA 1.65 V 0.24 0.45 0.45 VOL IOL = 8 mA 2.3 V 0.3 0.7 0.7 V IOL = 12 mA 2.7 V 0.4 0.4 0.4 IOL = 24 mA 3V 0.55 0.55 0.55 II VI = 5.5 V or GND 3.6 V ±1 ±5 ±5 µA Ioff VI or VO = 5.5 V 0 ±4 ±10 ±10 µA IOZ VI = 0 to 5.5 V 3.6 V ±1 ±10 ±10 µA VI = VCC or GND 1.5 10 10 ICC IO = 0 3.6 V µA A 3.6 V ≤ VI ≤ 5.5 V† 1.5 10 10 One input at VCC − 0.6 V, ∆ICC Other inputs at VCC or 2.7 V to 3.6 V 500 500 500 µA GND Ci VI = VCC or GND 3.3 V 4 pF Co VO = VCC or GND 3.3 V 5.5 pF † This applies in the disabled state only. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC574A VCC −55 TO 125°C UNIT MIN MAX 2.7 V 150 fclock Clock frequency MHz 3.3 V ± 0.3 V 150 2.7 V 3.3 tw Pulse duration, CLK high or low ns 3.3 V ± 0.3 V 3.3 2.7 V 2 tsu Setup time, data before CLK↑ ns 3.3 V ± 0.3 V 2 2.7 V 2 th Hold time, data after CLK↑ ns 3.3 V ± 0.3 V 2 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVC574A, SN74LVC574A OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC574A FROM TO PARAMETER VCC −55 TO 125°C UNIT (INPUT) (OUTPUT) MIN MAX 2.7 V 150 fmax MHz 3.3 V ± 0.3 V 150 2.7 V 8 tpd CLK Q ns 3.3 V ± 0.3 V 1 7 2.7 V 9 ten OE Q ns 3.3 V ± 0.3 V 1 7.5 2.7 V 7 tdis OE Q ns 3.3 V ± 0.3 V 0.5 6.4 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC574A VCC TA = 25°C −40 TO 85°C −40 TO 125°C UNIT MIN TYP MAX MIN MAX MIN MAX 1.8 V ± 0.15 V 55 55 40 2.5 V ± 0.2 V 95 95 80 fclock Clock frequency MHz 2.7 V 150 150 150 3.3 V ± 0.3 V 150 150 150 1.8 V ± 0.15 V 9 9 9 2.5 V ± 0.2 V 4 4 4 tw Pulse duration, CLK high or low ns 2.7 V 3.3 3.3 3.3 3.3 V ± 0.3 V 3.3 3.3 3.3 1.8 V ± 0.15 V 6 6 6 2.5 V ± 0.2 V 4 4 4 tsu Setup time, data before CLK↑ ns 2.7 V 2 2 2 3.3 V ± 0.3 V 2 2 2 1.8 V ± 0.15 V 4 4 4 2.5 V ± 0.2 V 2 2 2 th Hold time, data after CLK↑ ns 2.7 V 1.5 1.5 1.5 3.3 V ± 0.3 V 1.5 1.5 1.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LVC574A, SN74LVC574A OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC574A FROM TO PARAMETER VCC TA = 25°C −40 TO 85°C −40 TO 125°C UNIT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX 1.8 V ± 0.15 V 55 55 40 2.5 V ± 02 V 95 95 80 fmax MHz 2.7 V 150 150 150 3.3 V ± 0.3 V 150 150 150 1.8 V ± 0.15 V 1.0 7.1 21.5 1 21.6 1.0 21.6 2.5 V ± 0.2 V 1.0 4.9 10.0 1 10.5 1.0 10.5 tpd CLK Q ns 2.7 V 1.0 5.0 7.8 1 8 1.0 8.0 3.3 V ± 0.3 V 2.2 4.6 6.8 2.2 7 2.2 7.0 1.8 V ± 0.15 V 1.0 6.6 19.0 1 19.5 1.0 19.5 2.5 V ± 0.2 V 1.0 4.8 10.0 1 10.5 1.0 10.5 ten OE Q ns 2.7 V 1.0 5.5 8.3 1 8.5 1.0 8.5 3.3 V ± 0.3 V 1.5 4.4 7.3 1.5 7.5 1.5 7.5 1.8 V ± 0.15 V 1.0 5.4 18.3 1 18.8 1.0 18.8 2.5 V ± 0.2 V 1.0 3.0 7.3 1 7.8 1.0 7.8 tdis OE Q ns 2.7 V 1.0 4.0 6.8 1 7 1.0 7.3 3.3 V ± 0.3 V 1.7 3.9 6.2 1.7 6.4 1.7 6.6 tsk(o) 3.3 V ± 0.3 V 1 1 ns operating characteristics, TA = 25°C TEST PARAMETER VCC TYP UNIT CONDITIONS 1.8 V 25 Outputs enabled 2.5 V 29 3.3 V 30 Cpd Power dissipation capacitance per flip−flop f = 10 MHz pF 1.8 V 9 Outputs disabled 2.5 V 9 3.3 V 11 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVC574A, SN74LVC574A OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION VLOAD RL S1 Open From Output TEST S1 Under Test GND tPLH/tPHL Open CL RL tPLZ/tPZL VLOAD (see Note A) tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VM VLOAD CL RL V∆ VI tr/tf 1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V 2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V 2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V 3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V VI Timing Input VM 0V tw VI tsu th VI Input VM VM Data Input VM VM 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VI VI VM VM Output Input VM VM Control 0V 0V tPLH tPHL tPZL tPLZ Output VOH VLOAD/2 Waveform 1 Output VM VM VM S1 at VLOAD VOL + V∆ VOL (see Note B) VOL tPHL tPLH tPZH tPHZ VOH Output VOH VM VM Waveform 2 VOH − V∆ Output VM S1 at GND VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54LVC574A, SN74LVC574A OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Type Drawing Qty 5962-9757601Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-9757601QRA ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type 5962-9757601QSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type SN74LVC574ADBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI SN74LVC574ADBR ACTIVE SSOP DB 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574ADW ACTIVE SOIC DW 20 25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574AGQNR ACTIVE BGA MI GQN 20 1000 TBD SNPB Level-1-240C-UNLIM CROSTA R JUNI OR SN74LVC574AN ACTIVE PDIP N 20 20 Pb-Free CU NIPDAU N / A for Pkg Type (RoHS) SN74LVC574ANE4 ACTIVE PDIP N 20 20 Pb-Free CU NIPDAU N / A for Pkg Type (RoHS) SN74LVC574ANSR ACTIVE SO NS 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574APW ACTIVE TSSOP PW 20 70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574APWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI SN74LVC574APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574APWT ACTIVE TSSOP PW 20 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574APWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM no Sb/Br) SN74LVC574ARGYR ACTIVE QFN RGY 20 1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR no Sb/Br) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Type Drawing Qty SN74LVC574ARGYRG4 ACTIVE QFN RGY 20 1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR no Sb/Br) SN74LVC574AZQNR ACTIVE BGA MI ZQN 20 1000 Green (RoHS & SNAGCU Level-1-260C-UNLIM CROSTA no Sb/Br) R JUNI OR SNJ54LVC574AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type SNJ54LVC574AJ ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SNJ54LVC574AW ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN NO. OF A B 18 17 16 15 14 13 12 TERMINALS ** MIN MAX MIN MAX 0.342 0.358 0.307 0.358 19 11 20 (8,69) (9,09) (7,80) (9,09) 20 10 0.442 0.458 0.406 0.458 28 (11,23) (11,63) (10,31) (11,63) 21 9 B SQ 0.640 0.660 0.495 0.560 22 8 44 (16,26) (16,76) (12,58) (14,22) A SQ 23 7 0.739 0.761 0.495 0.560 52 (18,78) (19,32) (12,58) (14,22) 24 6 0.938 0.962 0.850 0.858 68 (23,83) (24,43) (21,6) (21,8) 25 5 1.141 1.165 1.047 1.063 84 (28,99) (29,59) (26,6) (27,0) 26 27 28 1 2 3 4 0.020 (0,51) 0.080 (2,03) 0.010 (0,25) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.045 (1,14) 0.022 (0,54) 0.035 (0,89) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°– 8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°– 8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065 /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,65 0,10 M 0,19 14 8 0,15 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 1,20 MAX 0,15 0,10 0,05 PINS ** 8 14 16 20 24 28 DIM A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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