This file is raw output from pdftotext and may not be ideal for distribution. If you are a maintainer for Hackipedia, please sit down when you have time and clean this text version up. Source PDF: /mnt/fw-js/docs/Hardware/Electronics/JTAG/Xilinx JTAG Schematic [2].pdf Like all conversions the text below should be fully readable as UTF-8 unicode text. --------------------------------------------------------------- 5 4 3 2 1 R1 100 D2 D1 VCC Sense (15) 2 1 2 1 VCC 1N5817 R13 1N5817 1K R8 D D C5 5.1K 0.01uF GND R7 300 CLK (3) U1 R4 300 2 3 R9 TDO/D/P 1A 1Y R10 100 DIN (2) 5 2A 2Y 6 TDI/DIN 9 8 R11 100 3A 3Y TCK/ CCLK 12 11 R12 100 4A 4Y TMS/PROG R3 300 100 PROG (6) 1 1OE 4 2OE 10 C4 C3 C2 C1 R5 300 3OE 100pF 100pF 100pF 100pF 13 4OE C C TMS_IN (4) 14 VCC GND 7 R6 300 74HC125 CTRL (5) R14 100 U2 R2 100 2 1A 1Y 3 GENERAL DESCRIPTION 5 6 DONE (13) 9 2A 2Y 8 The 74HC/HCT125 are high-speed Si-gate CMOS devices and 3A 3Y 12 4A 4Y 11 are pin compatible with low power Schottky TTL (LSTTL). 1 They are specified in compliance with JEDEC standard no. 7A. 1OE GND (20) 4 2OE The 74HC/HCT125 are four non-inverting buffer/line drivers with 10 B 13 3OE 4OE 3-state outputs. The 3-state outputs (nY) are controlled B 14 7 by the output enable input (nOE). A HIGH at nOE causes the GND (25) VCC GND outputs to assume a HIGH impedance OFF-state. 74HC125 The “125” is identical to the “126” but has active LOW enable D6 (8) inputs. BUSY (11) PE (12) A A SHIELD Title JTAG Cable Size Document Number Rev A 1 Date: Sheet 1 of 1 0 5 4 3 2 1