This file is raw output from pdftotext and may not be ideal for distribution. If you are a maintainer for Hackipedia, please sit down when you have time and clean this text version up. Source PDF: /mnt/main/jmc-storage/docs/Hardware/Audio codecs/Cirrus Logic/Cirrus Logic CS4923-9 Multi-Channel Digital Audio Decoders.pdf Like all conversions the text below should be fully readable as UTF-8 unicode text. --------------------------------------------------------------- CS4923/4/5/6/7/8/9 Multi-Channel Digital Audio Decoders l CS4923/4/5/6/7/8 features Description — Optional Virtual 3D Output The CS4923/4/5/6/7/8 is a family of multi-channel digital — Simulated Surround and Programmable Effects audio decoders, with the exception of the CS4929 as the — Real Time Autodetection of Dolby Digital®, only stereo digital audio decoder. The CS4923/4/5/6 are DTS®, MPEG Multi-Channel and PCM designed for Dolby Digital and MPEG-2 Stereo decoding. In addition the CS4925 adds MPEG-2 multi-channel decoding — Flexible 6-channel master or slave output capability and the CS4926 provides DTS decoding. The l CS4923/4/5/6/7/8/9 features CS4927 is an MPEG-2 multi-channel decoder and the — IEC60958/61937 transmitter for compressed- CS4928 is a DTS multi-channel decoder. The CS4929 is an data or linear-PCM output AAC 2-channel and MPEG-2 stereo decoder. Each one of — Dedicated 8 kilobyte input buffer the CS4923/4/5/6/7/8/9 provides a complete and flexible solution for multi-channel (or stereo in the case of the — DAC clock via analog phase-locked loop CS4929) audio decoding in home A/V receiver/amplifiers, — Dedicated byte wide or serial host interface DVD movie players, out-board decoders, laser-disc players, — Multiple compressed data input modes HDTV sets, head-end decoders, set-top boxes, and similar — PES layer decode for A/V synchronization products. — 96-kHz-capable PCM I/O, master or slave Cirrus Logic’s Crystal Audio Division provides a complete set — Optional external memory and auto-boot of audio decoder and auxiliary audio DSP application programs for various applications. For all complementary — +3.3-V CMOS low-power, 44-pin package analog and digital audio I/O, Crystal Audio also provides a l CS4923/4/5/6 features complete set of high-quality audio peripherals including: — Capable of Dolby Digital® Group A Performance multimedia CODECs, stereo A/D and D/A converters and — Dolby bass manager and crossover filters IEC60958 interfaces. Of special note, the CS4226 is a complementary CODEC providing a digital receiver, stereo — Dolby Surround Pro Logic® Decoding A/D converters, and six 20-bit DACs in one package. l CS4925/7: MPEG-2 Multi-Channel Decoder ORDERING INFORMATION l CS4926/8: DTS Multi-Channel Decoder CS4923xx-CL 44-pin PLCC (xx = ROM revision) l CS4929: AAC 2-Channel (Low Complexity) CRD4923 Reference design with CS4226 and MPEG-2 Stereo Decoder CDB4923 Evaluation board RD, WR, SCDIO, DATA7:0, R/W, DS, SCDOUT, EMAD7:0, EMOE, EMWR, PSEL, A0, A1, ABOOT, EXTMEM, RESET GPIO7:0 CS GPIO11 GPIO10 GPIO9 SCCLK SCDIN INTREQ GPIO8 CMPDAT, DD SDATAN2 Compressed Parallel or Serial Host Interface DC Data Input CMPCLK, Interface Framer SCLKN2 Shifter 24-Bit CMPREQ, DSP Processing MCLK LRCLKN2 Input Buffer RAM RAM SCLK SCLKN1, Digital Controller Program Data Output STCCLK2 Memory Memory LRCLK Audio RAM Formatter LRCLKN1 Input ROM Output AUDATA[2.0] ROM SDATAN1 Interface RAM Input Program Data Buffer Buffer Memory Memory CLKIN PLL XMT958 STC CLKSEL Clock Manager FILT2 FILT1 VA AGND DGND[3:1] VD[3:1] This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 1999 AUG ‘99 P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved) (512) 445 7222 FAX: (512) 445 7581 DS262F2 http://www.cirrus.com 1 CS4923/4/5/6/7/8/9 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 ABSOLUTE MAXIMUM RATINGS ............................................................................................ 4 RECOMMENDED OPERATING CONDITIONS ........................................................................ 4 DIGITAL D.C. CHARACTERISTICS .......................................................................................... 4 POWER SUPPLY CHARACTERISTICS ................................................................................... 4 SWITCHING CHARACTERISTICS—RESET ............................................................................ 5 SWITCHING CHARACTERISTICS—CMPDAT, CMPCLK........................................................ 6 SWITCHING CHARACTERISTICS—CLKIN ............................................................................. 7 SWITCHING CHARACTERISTICS—INTEL® HOST MODE..................................................... 8 SWITCHING CHARACTERISTICS—MOTOROLA® HOST MODE ........................................ 10 SWITCHING CHARACTERISTICS—DIGITAL AUDIO INPUT................................................ 16 SWITCHING CHARACTERISTICS—DIGITAL AUDIO OUTPUT............................................ 18 2. FAMILY OVERVIEW .............................................................................................................. 20 2.1 Multi-channel Decoder Family of Parts ............................................................................ 21 2.2 Document Strategy .......................................................................................................... 21 2.2.1 Hardware Documentation ............................................................................... 22 2.2.2 CS4923/4/5/6/7/8/9 Application Code User’s Guides ..................................... 22 2.3 Using the CS4923/4/5/6/7/8/9 .......................................................................................... 22 3. TYPICAL CONNECTION DIAGRAMS ................................................................................... 23 3.1 Multiplexed Pins ............................................................................................................... 23 3.2 Termination Requirements ............................................................................................... 24 3.3 Phase Locked Loop Filter ................................................................................................ 24 4. POWER .................................................................................................................................. 31 4.1 Decoupling ....................................................................................................................... 31 4.2 Analog Power Conditioning .............................................................................................. 31 4.3 Pads ................................................................................................................................. 31 5. CLOCKING ............................................................................................................................. 32 6. CONTROL .............................................................................................................................. 33 6.1 Boot and Control Mode Overview .................................................................................... 33 6.2 Parallel Host Interface ...................................................................................................... 34 6.2.1 Intel Parallel Host Mode .................................................................................. 34 6.2.2 Motorola Parallel Host Mode ........................................................................... 36 6.3 SPI Serial Host Interface .................................................................................................. 36 6.3.1 SPI Write ......................................................................................................... 37 6.3.2 SPI Read ......................................................................................................... 37 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Dolby, Dolby Digital, and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corporation. Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductor. All other names are trademarks, registered trademarks, or service marks of their respective companies. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 DS262F2 CS4923/4/5/6/7/8/9 6.4 I2C Serial Host Interface .................................................................................................. 39 6.4.1 I2C Write ......................................................................................................... 39 6.4.2 I2C Read ......................................................................................................... 39 6.5 External Memory .............................................................................................................. 41 6.5.1 External Memory and Autoboot ...................................................................... 43 7. DIGITAL INPUT & OUTPUT .................................................................................................. 44 7.1 Digital Audio Formats ....................................................................................................... 44 7.2 Digital Audio Input Port .................................................................................................... 46 7.3 Compressed Data Input Port ........................................................................................... 46 7.4 Parallel Digital Audio Data Input ...................................................................................... 46 7.5 Digital Audio Output Port ................................................................................................. 47 7.5.1 IEC60958 Output ............................................................................................ 48 8. PIN DESCRIPTIONS .............................................................................................................. 49 9. PACKAGE DIMENSIONS ...................................................................................................... 54 LIST OF FIGURES Figure 1. RESET Timing .................................................................................................................. 5 Figure 2. Serial Compressed Data Timing ....................................................................................... 6 Figure 3. CLKIN with CLKSEL = VSS = PLL Enable........................................................................ 7 Figure 4. CLKIN with CLKSEL = VD = PLL Bypass ......................................................................... 7 Figure 5. Intel Parallel Host Mode Read Cycle................................................................................. 9 Figure 6. Intel Parallel Host Mode Write Cycle................................................................................. 9 Figure 7. Motorola Parallel Host Mode Read Cycle ....................................................................... 11 Figure 8. Motorola Parallel Host Mode Write Cycle........................................................................ 11 Figure 9. SPI Control Port Timing................................................................................................... 13 Figure 10. I2C Control Port Timing ................................................................................................. 15 Figure 11. Digital Audio Input, Data and Clock Timing................................................................... 17 Figure 12. Digital Audio Output, Data and Clock Timing ................................................................ 19 Figure 13. I2C Control..................................................................................................................... 25 Figure 14. I2C Control with External Memory ................................................................................. 26 Figure 15. SPI Control .................................................................................................................... 27 Figure 16. SPI Control with External Memory ................................................................................ 28 Figure 17. Intel Parallel Control Mode ............................................................................................ 29 Figure 18. Motorola Parallel Control Mode..................................................................................... 30 Figure 19. SPI Timing..................................................................................................................... 38 Figure 20. I2C Timing ..................................................................................................................... 40 Figure 21. External Memory Interface ............................................................................................ 42 Figure 22. Run-Time Memory Access ............................................................................................ 42 Figure 23. Autoboot Timing Diagram.............................................................................................. 43 Figure 24. I2S Format ..................................................................................................................... 45 Figure 25. Left Justified Format...................................................................................................... 45 Figure 26. Right Justified................................................................................................................ 45 Figure 27. Multi-Channel Format (M == 20) ................................................................................... 45 LIST OF TABLES Table 1. Silicon Revisions .............................................................................................................. 20 Table 2. Host Modes ...................................................................................................................... 33 Table 3. Host Memory Map ............................................................................................................ 34 Table 4. Intel Parallel Host Mode Pin Assignments........................................................................ 34 Table 5. Parallel Input/Output Registers......................................................................................... 35 Table 6. Motorola Parallel Host Mode Pin Assignments ................................................................ 36 Table 7. SPI Serial Mode Pin Assignments.................................................................................... 36 Table 8. I2C Serial Mode Pin Assignments .................................................................................... 39 Table 9. Memory Interface Pins...................................................................................................... 41 Table 10. Digital Audio Input Port................................................................................................... 46 Table 11. Compressed Data Input Port .......................................................................................... 46 Table 12. Digital Audio Output Port ................................................................................................ 47 Table 13. MCLK/SCLK Master Mode Ratios .................................................................................. 47 DS262F2 3 CS4923/4/5/6/7/8/9 1. CHARACTERISTICS AND SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; all voltages with respect to 0 V) Parameter Symbol Min Max Unit DC power supplies: Positive digital VD –0.3 3.63 V Positive analog VA –0.3 3.63 V ||VA| – |VD|| - 0.4 V Input current, any pin except supplies Iin - ±10 mA Digital input voltage VIND –0.3 5.5 V Ambient operating temperature (power applied) TAmax –55 125 °C Storage temperature Tstg –65 150 °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; all voltages with respect to 0 V) Parameter Symbol Min Typ Max Unit DC power supplies: Positive digital VD 3.13 3.3 3.47 V Positive analog VA 3.13 3.3 3.47 V ||VA| – |VD|| - - 0.4 V Ambient operating temperature TA 0 - 70 °C DIGITAL D.C. CHARACTERISTICS (TA = 25 °C; VA, VD[3:1] = 3.3 V ±5%; measurements performed under static conditions.) Parameter Symbol Min Typ Max Unit High-level input voltage VIH 2.0 - - V Low-level input voltage VIL - - 0.8 V High-level output voltage at IO = –4.0 mA VOH VD × 0.9 - - V Low-level output voltage at IO = 4.0 mA VOL - - VD × 0.1 V Input leakage current Iin - - 1.0 µA POWER SUPPLY CHARACTERISTICS (TA = 25 °C; VA, VD[3:1] = 3.3 V ±5%; measurements performed under operating conditions) Parameter Symbol Min Typ Max Unit Power supply current: Digital operating: VD[3:1] - 225 435 mA Analog operating: VA - 4 8 mA 4 DS262F2 CS4923/4/5/6/7/8/9 SWITCHING CHARACTERISTICS—RESET (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)z Parameter Symbol Min Max Unit RESET minimum pulse width low Trstl 100 - ns All bidirectional pins high-Z after RESET low Trst2z - 50 ns Configuration bits setup before RESET high Trstsu 50 - ns Configuration bits hold after RESET high Trsthld 15 - ns RESET RD, WR, PSEL, ABOOT All Bidirectional Outputs Trstsu Trsthld Trst2z Trstl Figure 1. RESET Timing DS262F2 5 CS4923/4/5/6/7/8/9 SWITCHING CHARACTERISTICS—CMPDAT, CMPCLK (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Parameter Symbol Min Max Unit Serial compressed data clock CMPCLK period Tcmpclk 37 - ns CMPDAT setup before CMPCLK high Tcmpsu 5 - ns CMPDAT hold after CMPCLK high Tcmphld 3 - ns CMPCLK CMPDAT Tcmpsu Tcmphld Tcmpclk Figure 2. Serial Compressed Data Timing 6 DS262F2 CS4923/4/5/6/7/8/9 SWITCHING CHARACTERISTICS—CLKIN (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Parameter Symbol Min Max Unit CLKIN period for internal DSP clock mode Tclki 20 3800 ns CLKIN high time for internal DSP clock mode Tclkih 8 ns CLKIN low time for internal DSP clock mode Tclkil 8 ns CLKIN period for external DSP clock mode Tclke 20 25 ns CLKIN high time for external DSP clock mode Tclkeh 9 ns CLKIN low time for external DSP clock mode Tclkel 9 ns CLKIN Tclkih Tclkil Tclki Figure 3. CLKIN with CLKSEL = VSS = PLL Enable CLKIN Tclkeh Tclkel Tclke Figure 4. CLKIN with CLKSEL = VD = PLL Bypass DS262F2 7 CS4923/4/5/6/7/8/9 SWITCHING CHARACTERISTICS—INTEL® HOST MODE (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Parameter Symbol Min Max Unit Address setup before CS and RD low or CS and WR low Tias 5 - ns Address hold time after CS and RD low or CS and WR low Tiah 5 - ns Delay between RD then CS low or CS then RD low Ticdr 0 ∞ ns Data valid after CS and RD low Tidd - 20 ns CS and RD low for read (Note 1) Tirpw DCLK + 10 - ns Data hold time after CS or RD high Tidhr 5 - ns Data high-Z after CS or RD high (Note 2) Tidis - 15 ns CS or RD high to CS and RD low for next read (Note 1) Tird 2*DCLK + 10 - ns CS or RD high to CS and WR low for next write (Note 1) Tirdtw 2*DCLK + 10 - ns Delay between WR then CS low or CS then WR low Ticdw 0 ∞ ns Data setup before CS or WR high Tidsu 20 - ns CS and WR low for write (Note 1) Tiwpw DCLK + 10 - ns Data hold after CS or WR high Tidhw 5 - ns CS or WR high to CS and RD low for next read (Note 1) Tiwtrd 2*DCLK + 10 - ns CS or WR high to CS and WR low for next write (Note 1) Tiwd 2*DCLK + 10 - ns Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can be defined as follows: External CLKIN Mode: DCLK == CLKIN/3 before and during boot DCLK == CLKIN after boot Internal Clock Mode: DCLK == 10MHz before and during boot, i.e. DCLK == 100ns DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see CS4923/4/5/6/7/8/9 Hardware User’s Guide for more information) 2. This specification is characterized but not production tested. 8 DS262F2 CS4923/4/5/6/7/8/9 A1:0 Tiah DATA7:0 Tias Tidhr Tidd CS Ticdr Tidis WR Tirpw Tird Tirdtw RD Figure 5. Intel Parallel Host Mode Read Cycle A1:0 Tiah DATA7:0 Tias Tidhw CS Ticdw Tidsu RD Tiwpw Tiwd Tiwtrd WR Figure 6. Intel Parallel Host Mode Write Cycle DS262F2 9 CS4923/4/5/6/7/8/9 SWITCHING CHARACTERISTICS—MOTOROLA® HOST MODE (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Parameter Symbol Min Max Unit Address setup before CS and DS low Tmas 5 - ns Address hold time after CS and DS low Tmah 5 - ns Delay between DS then CS low or CS then DS low Tmcdr 0 ∞ ns Data valid after CS and DS low with R/W high Tmdd - 20 ns CS and DS low for read (Note 3) Tmrpw DCLK + 10 - ns Data hold time after CS or DS high after read Tmdhr 5 - ns Data high-Z after CS or DS high low after read (Note 4) Tmdis - 15 ns CS or DS high to CS and DS low for next read (Note 3) Tmrd 2*DCLK + 10 - ns CS or DS high to CS and DS low for next write (Note 3) Tmrdtw 2*DCLK + 10 - ns Delay between DS then CS low or CS then DS low Tmcdw 0 ∞ ns Data setup before CS or DS high Tmdsu 20 - ns CS and DS low for write (Note 3) Tmwpw DCLK + 10 - ns R/W setup before CS or DS low Tmrwsu 5 - ns R/W hold time after CS or DS high Tmrwhld 5 - ns Data hold after CS or DS high Tmdhw 5 - ns CS or DS high to CS and DS low with R/W high for next read Tmwtrd 2*DCLK + 10 - ns (Note 3) CS or DS high to CS and DS low for next write (Note 3) Tmwd 2*DCLK + 10 - ns Notes: 3. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can be defined as follows: External CLKIN Mode: DCLK == CLKIN/3 before and during boot DCLK == CLKIN after boot Internal Clock Mode: DCLK == 10MHz before and during boot, i.e. DCLK == 100ns DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see CS4923/4/5/6/7/8/9 Hardware Users Guide for more information) 4. This specification is characterized but not production tested. 10 DS262F2 CS4923/4/5/6/7/8/9 A1:0 Tmah DATA7:0 Tmas Tmdhr Tmdd CS Tmrwsu Tmcdr Tmdis Tmrwhld R/W Tmrpw Tmrd Tmrdtw DS Figure 7. Motorola Parallel Host Mode Read Cycle A1:0 Tmas Tmah DATA7:0 Tmdsu Tmdhw CS Tmcdw Tmwpw Tmrwhld R/W Tmrwsu Tmwd Tmwtrd DS Figure 8. Motorola Parallel Host Mode Write Cycle DS262F2 11 CS4923/4/5/6/7/8/9 SWITCHING CHARACTERISTICS—SPI CONTROL PORT (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Parameter Symbol Min Max Units SCCLK clock frequency (Note 5) fsck - 2000 kHz CS falling to SCCLK rising tcss 20 - ns Rise time of SCCLK line (Note 11) tr - 50 ns Fall time of SCCLK lines (Note 11) tf - 50 ns SCCLK low time tscl 150 - ns SCCLK high time tsch 150 - ns Setup time SCDIN to SCCLK rising tcdisu 50 - ns Hold time SCCLK rising to SCDIN (Note 6) tcdih 50 - ns Transition time from SCCLK to SCDOUT valid (Note 7) tscdov - 40 ns Time from SCCLK rising to INTREQ rising (Note 8) tscrh - 200 ns Rise time for INTREQ (Note 8) trr - (Note ns 10) Hold time for INTREQ from SCCLK rising (Note 9, 11) tscrl 0 - ns Time from SCCLK falling to CS rising tsccsh 20 - ns High time between active CS tcsht 200 - ns Time from CS rising to SCDOUT high-Z (Note 11) tcscdo 10 ns Notes: 5. The specification fsck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the software. The relevant application code user’s manual should be consulted for the software speed limitations. 6. Data must be held for sufficient time to bridge the 50 ns transition time of SCCLK. 7. SCDOUT should not be sampled during this time period. 8. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the second-to-last bit of the last byte of data during a read operation as shown. 9. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat this condition as a new read transaction. Raise chip select to end the current read transaction and then drop it, followed by the 7-bit address and the R/W bit (set to 1 for a read) to start a new read transaction. 10. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time. 11. This time is by design and not tested. 12 DS262F2 DS262F2 tsccsh CS tcsht tcss tscl 0 1 2 6 7 0 5 6 7 SCCLK t t tsch r f SCDIN A6 A5 A0 R/W MSB LSB A6 t cdisu t cdih SCDOUT MSB LSB tri-state tscdov tscdov tcscdo INTREQ tscrh tscrl CS4923/4/5/6/7/8/9 Figure 9. SPI Control Port Timing 13 CS4923/4/5/6/7/8/9 SWITCHING CHARACTERISTICS— I2C® CONTROL PORT (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Parameter Symbol Min Max Units SCCLK clock frequency (Note 12) fscl 400 kHz Bus free time between transmissions tbuf 4.7 µs Start-condition hold time (prior to first clock pulse) thdst 4.0 µs Clock low time tlow 1.2 µs Clock high time thigh 1.0 µs SCDIO setup time to SCCLK rising tsud 250 ns SCDIO hold time from SCCLK falling (Note 13) thdd 0 µs Rise time of SCCLK (Note 14), (Note 18) tr 50 ns Fall time of SCCLK (Note 18) tf 300 ns Time from SCCLK falling to CS4923/4/5/6/7/8/9 ACK tsca 40 ns Time from SCCLK falling to SCDIO valid during read operation tscsdv 40 ns Time from SCCLK rising to INTREQ rising (Note 15) tscrh 200 ns Hold time for INTREQ from SCCLK rising (Note 16) tscrl 0 ns Rise time for INTREQ trr (Note ns 17) Setup time for stop condition tsusp 4.7 µs Notes: 12. The specification fscl indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the software. The relevant application code user’s manual should be consulted for the software speed limitations. 13. Data must be held for sufficient time to bridge the 300-ns transition time of SCCLK. This hold time is by design and not tested. 14. This rise time is shorter than that recommended by the I2C specifications. For more information, see the section on SCP communications. 15. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the last data bit of the last byte of data during a read operation as shown. 16. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat this condition as a new read transaction. Send a new start condition followed by the 7-bit address and the R/W bit (set to 1 for a read). This time is by design and is not tested. 17. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time. 18. This time is by design and not tested. 14 DS262F2 DS262F2 stop start stop SCDIO A6 A5 A0 R/W ACK MSB LSB ACK tbuf t scsdv tsud 0 1 6 7 8 0 7 8 SCCLK t scrl tsusp thdst tlow t hdd thigh tr tf tsca INTREQ tscrh CS4923/4/5/6/7/8/9 Figure 10. I2C Control Port Timing 15 CS4923/4/5/6/7/8/9 SWITCHING CHARACTERISTICS—DIGITAL AUDIO INPUT (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Parameter Symbol Min Max Unit SCLKN1(2) period for both Master and Slave mode (Note 19) Tsclki 40 - ns SCLKN1(2) duty cycle for Master and Slave mode (Note 19) 45 55 % Master Mode (Note 19,20) LRCLKN1(2) delay after SCLKN1(2) transition (Note 21) Tlrds - 10 ns SDATAN1(2) setup to SCLKN1(2) transition (Note 22) Tsdsum 10 - ns SDATAN1(2) hold time after SCLKN1(2) transition (Note 22) Tsdhm 5 - ns Slave Mode (Note 23) Time from active edge of SCLKN1(2) to LRCLKN1(2) transition Tstlr 10 - ns Time from LRCLKN1(2) transition to SCLKN1(2) active edge Tlrts 10 - ns SDATAN1(2) setup to SCLKN1(2) transition (Note 22) Tsdsus 5 - ns SDATAN1(2) hold time after SCLKN1(2) transition (Note 22) Tsdhs 5 - ns Notes: 19. Master mode timing specifications are characterized, not production tested. 20. Master mode is defined as the CS4923 driving LRCLKN1(2) and SCLKN1(2). Master or Slave mode can be programmed. 21. This timing parameter is defined from the non-active edge of SCLKN1(2). The active edge of SCLKN1(2) is the point at which the data is valid. 22. This timing parameter is defined from the active edge of SCLKN1(2). The active edge of SCLKN1(2) is the point at which the data is valid. 23. Slave mode is defined as SCLKN1(2) and LRCLKN1(2) being driven by an external source. 16 DS262F2 CS4923/4/5/6/7/8/9 MASTER MODE SCLKN1 SCLKN2 Tlrds Tsclki LRCLKN1 LRCLKN2 Tsdsum Tsdhm SDATAN1 SDATAN2 SLAVE MODE SCLKN1 SCLKN2 Tsclki Tlrts Tstlr LRCLKN1 LRCLKN2 Tsdsus Tsdhs SDATAN1 SDATAN2 Figure 11. Digital Audio Input, Data and Clock Timing DS262F2 17 CS4923/4/5/6/7/8/9 SWITCHING CHARACTERISTICS—DIGITAL AUDIO OUTPUT (TA = 25 °C; VA, VD = 3.3 V ±5%; measurements performed under static conditions.) Parameter Symbol Min Max Unit MCLK period (Note 24) Tmclk 40 - ns MCLK duty cycle (Note 24) 40 60 % SCLK period for Master or Slave mode (Note 25) Tsclk 40 - ns SCLK duty cycle for Master or Slave mode (Note 25) 45 55 % Master Mode (Note 25,26) SCLK delay from MCLK rising edge, MCLK as an input Tsdmi 15 ns SCLK delay from MCLK rising edge, MCLK as an output Tsdmo –5 10 ns LRCLK delay from SCLK transition (Note 27) Tlrds 10 ns AUDATA2–0 delay from SCLK transition (Note 27) Tadsm 10 ns Slave Mode (Note 28) Time from active edge of SCLKN1(2) to LRCLKN1(2) transition Tstlr 10 - ns Time from LRCLKN1(2) transition to SCLKN1(2) active edge Tlrts 10 - ns AUDATA2–0 delay from SCLK transition (Note 27,29) Tadss 15 ns Notes: 24. MCLK can be an input or an output. These specifications apply for both cases. 25. Master mode timing specifications are characterized, not production tested. 26. Master mode is defined as the CS4923 driving both SCLK and LRCLK. When MCLK is an input, it is divided to produce SCLK and LRCLK. 27. This timing parameter is defined from the non-active edge of SCLK. The active edge of SCLK is the point at which the data is valid. 28. Slave mode is defined as SCLK and LRCLK being driven by an external source. 29. This specification is characterized, not production tested. 18 DS262F2 CS4923/4/5/6/7/8/9 MCLK (Input) T mclk SCLK (Output) T sdmi MCLK (Output) T mclk SCLK (Output) T sdmo MASTER MODE SCLK Tsclk Tlrds LRCLK Tadsm AUDATA2:0 SLAVE MODE SCLK Tlrts Tsclk Tstlr LRCLK Tadss AUDATA2:0 Figure 12. Digital Audio Output, Data and Clock Timing DS262F2 19 CS4923/4/5/6/7/8/9 2. FAMILY OVERVIEW out when features are discussed within this The CS4923, CS4924, CS4925, CS4926, CS4927, document. The silicon revision for any chip can be CS4928 and the CS4929 are system on a chip determined by referencing Table 1 below. solutions for multi-channel (or stereo in the case of the CS4929) audio decompression and digital Revision B Revision D signal processing. Because the parts are primarily CS492301 CS492305 RAM-based, a download of application software is CS492401 CS492405 required each time the CS4923/4/5/6/7/8/9 is CS492501 CS492505 powered up. This document uses “download” and CS492603 CS492604 “code load” interchangeably. These terms should CS492705 CS492804 be interpreted as meaning the transfer of CS492906 application code into the internal Table 1. Silicon Revisions CS4923/4/5/6/7/8/9 memory from either an external microcontroller or through the autoboot These parts are generally targeted at two different procedure. market segments. The broadcast market where This document focuses on the electrical features audio/video (A/V) synchronization is required, and and characteristics of these parts. The different the outboard decoder markets where audio/video features are described from a hardware design synchronization is not required. The important perspective. It should be understood that not all of differentiation is the format in which the data will the features portrayed in this document are be received by the CS4923/4/5/6/7/8/9. In systems supported by all of the versions of application code where A/V synchronization is required from the available. The application user’s guides (see CS4923/4/5/6/7/8/9, the incoming data is typically section 2.2.2) should be consulted to confirm PES encoded. In an outboard decoder application which hardware features are supported by the the data typically comes in the IEC61937 format software. This document will be valuable to both (as specified by the DVD consortium). An the hardware designer and the system programmer. important point to remember is that the CS4923/4/5/6/7/8/9 will support both This data sheet covers the CS4923, CS4924, environments, but different downloads are required CS4925, CS4926, CS4927, CS4928 and CS4929. depending on the input data type. These parts are identical from an external electrical perspective. Internally each device has been Broadcast applications include (but are not limited tailored for supporting different decoding to) set top box applications, DVDs and digital TVs. standards. For this document CS4923/4/5/6/7/8/9 Outboard decoder applications include standalone has been replaced in certain places with CS492X decoders and audio/video receivers. Often times a for readability. Unless otherwise specified system may be a hybrid between an outboard CS492X should be interpreted as applying to the decoder and a broadcast system depending on its CS4923, CS4924, CS4925, CS4926, CS4927, functionality. CS4928 and CS4929. As discussed above, compressed audio can be There are two revisions of silicon commercially packed in IEC61937, PES, or elementary formats available. The features available on Revision D are depending on the decoder environment. Each for- a super-set of those features available on Revision mat is supported by a separate download of appli- B. Differences between the revisions are pointed cation code. Consult the relevant Application Code 20 DS262F2 CS4923/4/5/6/7/8/9 User’s Guide to determine which formats are sup- audio. Another code load can be used to support ported by a particular application. A brief descrip- stereo to 5.1 channel effects processing. tion of each format is presented below. CS4926 - DTS/Dolby® Multi-Channel Audio Elementary - an elementary bitstream consists only Decoder. The CS4926 supports both Dolby Digital of compressed audio data (e.g., strictly the Dolby and DTS, or Digital Theater Surround. For Dolby Digital bitstream); used primarily in broadcast en- Digital, post processing includes bass management vironments. and Dolby Pro Logic. The Dolby Digital code and PES - a Packetized Elementary Stream (PES) bit- DTS code take separate code downloads. Separate stream contains the elementary compressed audio downloads can also be used to support stereo to 5.1 stream and additional header information which channel effects processing and stereo MPEG can be used for A/V synchronization; used primari- decoding. ly in broadcast environments. CS4927 - MPEG-2 Multi-Channel Decoder. The IEC61937 - a method of packing compressed audio CS4927 supports MPEG-2 multi-channel decoding such that it can be delivered using a bi-phase en- and should be used in applications where Dolby coded signal (e.g., S/PDIF output signal from DVD Digital decoding is not necessary. For MPEG-2 player); used primarily for outboard decoders multi-channel decoding, post processing includes where A/V synchronization is not required. bass management and Dolby Pro Logic decoding. Another code load can be used to support stereo to 2.1 Multi-channel Decoder Family of Parts 5.1 channel effects processing. CS4923 - Dolby DigitalTM Audio Decoder. The CS4928 - DTS Multi-Channel Decoder. The CS4923 is the original member of the family and is CS4928 supports DTS multi-channel decoding and intended to be used if only Dolby Digital decoding should be used in applications where Dolby Digital is required. For Dolby Digital, post processing decoding is not necessary. For DTS multi-channel includes bass management, delays and Dolby Pro decoding, post processing includes bass Logic decoding. Separate downloads can also be management. Separate downloads can also be used used to support stereo to 5.1 channel effects to support stereo to 5.1 channel effects processing processing and stereo MPEG decoding. and stereo MPEG decoding. CS4924 - Dolby DigitalTM Source Product CS4929 - AAC 2-Channel, (Low Complexity) and Decoder. The CS4924 is the stereo version of the MPEG-2 Stereo Decoder. The CS4929 is capable CS4923 designed for source products such as of decoding both 2-channel AAC and MPEG-2 DVD, HDTV, and set-top boxes. Separate audio. The CS4929 supports elementary and PES downloads are available for stereo decode of Dolby formats. Digital and MPEG audio. 2.2 Document Strategy CS4925 - International Multi-Channel DVD Audio Decoder. The CS4925 supports both Dolby Multiple documents are needed to fully define, Digital and MPEG-2 multi-channel formats. For understand and implement the functionality of the both Dolby Digital and MPEG-2 multi-channel, CS4923/4/5/6/7/8/9. They can be split up into two post processing includes bass management and basic groups: hardware and application code Dolby Pro Logic decoding. Separate downloads are documentation. It should be noted that hardware available for decode of Dolby Digital and MPEG and application code are co-dependent and one can not successfully use the device without an DS262F2 21 CS4923/4/5/6/7/8/9 understanding of both. The ‘ANXXX’ notation MPEG Multi-Channel code including delays, bass denotes the application note number under which management, Pro Logic, and MPEG processing the respective user’s guide was released. features. 2.2.1 Hardware Documentation AN122 - DTS User’s Guide for the CS4926, CS4928. This document covers the features CS4923/4/5/6/7/8/9 Family Data Sheet - This available in the DTS code including bass document describes the electrical characteristics of management and DTS processing features. the device from timing to base functionality. This is the hardware designers tool to learn the part’s AN123 - Surround User’s Guide for the electrical and systems requirements. CS4923/4/5/6/7/8. This code covers the different Stereo PCM to surround effects processing code. AN115 - CS4923/4/5/6/7/8/9 Hardware User’s Optional appendices are available that document Guide - describes the functional aspects of the Crystal Original Surround, Circle Surround and device. An in depth description of communication, Logic 7. boot procedure, external memory and hardware configuration are given in this document. This AN140 - Broadcast Systems Guide for the document will be valuable to both the hardware CS4923/4/5/6/7/8/9. This guide describes all designer and the system programmer. application code (e.g. Dolby Digital, MPEG, AAC) designed for broadcast systems such as HDTV and 2.2.2 CS4923/4/5/6/7/8/9 Application Code set-top box receivers. This document also provides User’s Guides a discussion of broadcast system considerations The following application notes describe the and dependencies such as A/V synchronization and application codes used with the channel change procedures. CS4923/4/5/6/7/8/9. Whenever an application code 2.3 Using the CS4923/4/5/6/7/8/9 user’s guide is referred to, it should be assumed that No matter what application is being used on the one or more of the below documents are being chip, the following four steps are always followed referenced. The following list covers currently to use the CS4923/4/5/6/7/8/9 in system. released application notes. This list will grow with each new application released. For a current list of 1) Reset and/or Download Code - Detailed released user’s guides please see www.crystal.com information in AN115 and search for the part number. 2) Hardware Configuration - Detailed information AN120 - Dolby Digital User’s Guide for the in AN115 CS4923/4/5/6. This document covers the features 3) Application configuration - Detailed available in the Dolby Digital code including information in the appropriate Application delays, pink noise, bass management, Pro Logic, Code User’s guide PCM pass through and Dolby Digital processing 4) Kickstart - This is the “Go” command to the features. Optional appendices are available that CS492X once the system is properly document code for Dolby Virtual, Q-Surround and configured. Information can be found in the VMAx. appropriate Application Code User’s guide. AN121 - MPEG User’s Guide for the CS4925. This document covers the features available in the 22 DS262F2 CS4923/4/5/6/7/8/9 3. TYPICAL CONNECTION Some pins are designed to operate in one mode at DIAGRAMS power up, and serve a different purpose when the Six typical connection diagrams have been DSP is running. Other pins have functionality presented to illustrate using the device with the which can be controlled by the application running different communication modes available. They on the DSP. In order to better explain the behavior are as follows: of the part, the pins which are multiplexed have been given multiple names. Each name is specific Figure 13: I2C Control to the pin’s operation in a particular mode. Figure 14: I2C Control with External Memory Figure 15: SPI Control An example of this would be the use of pin 20 in Figure 16: SPI Control with External Memory one of the serial control modes. During the boot Figure 17: Intel Parallel Control Mode period of the CS492X, pin 20 is called ABOOT. Figure 18: Motorola Parallel Control Mode ABOOT is sampled on the rising edge of RESET. If ABOOT is high the host must download code to The following should be noted when viewing the the DSP. If ABOOT is low when sampled, the typical connection diagrams: CS492X goes into autoboot mode and loads itself The pins are grouped functionally in each of the with code by generating addresses and reading data typical connection diagrams. Please be aware that on EMAD[7:0]. When the device has been loaded the CS4923/4/5/6/7/8/9 symbol may appear with code and is running an application, however, differently in each diagram. pin 20 is called INTREQ. INTREQ is an open drain The external memory interface is only supported output used to inform the host that the DSP has an when a serial communication mode has been outgoing message which should be read. chosen. In this document, pins will be referred to by their The typical connection diagrams demonstrate the functionality. The section “Pin Descriptions” on PLL being used (CLKSEL is pulled low). To page 49 describes each pin of the CS492X and lists enable external CLKIN, CLKSEL should be pulled all of its names. Please refer to the Pin Descriptions high. The system designer must be aware that section when exact pin numbers are in question. certain software features may not be available if The device has 12 general purpose input and output external CLKIN is used as the DSP must run (GPIO[11:0]) pins that all have multiple slower when external CLKIN is used. The system functionality. While in one of the parallel designer should also be aware of additional duty communication modes (see section 6.2), these pins cycle requirements when using external CLKIN are used to implement the parallel host mode. It is highly suggested that the system communication interface. While in one of the serial designer take advantage of the PLL and pull host modes these pins are used to implement an CLKSEL low. external memory interface. Alternatively while in one of the serial host modes these pins could be 3.1 Multiplexed Pins used for another general purpose if the application The CS4923/4/5/6/7/8/9 family of digital signal code has been programmed to support the special processors (DSPs) incorporate a large amount of purpose. In this document the pins are referenced flexibility into a 44 pin package. Because of the by the name corresponding to their particular use. high degree of integration, many of these pins are Sometimes GPIO[11:0], or some subset thereof, is internally multiplexed to serve multiple purposes. used when referring to the pins in a general sense. DS262F2 23 CS4923/4/5/6/7/8/9 3.2 Termination Requirements information). For the explicit termination The CS4923/4/5/6/7/8/9 incorporates open drain requirements of each communication mode please pins which must be pulled high for proper see the typical connection diagrams. operation. INTREQ (pin 20) is always an open Generally a 4.7k Ohm resistor is recommended for drain pin which requires a pull-up for proper open drain pins while a 10k Ohm resistor is operation. When in the I2C serial communication sufficient for the GPIO pins and unused inputs. mode, the SCDIO signal (pin 19) is open drain and thus requires a pull-up for proper operation. 3.3 Phase Locked Loop Filter The internal phase locked loop (PLL) of the Due to the internal, multiplexed design of the pins, CS4923/4/5/6/7/8/9 requires an external filter for certain signals may or may not require termination successful operation. The topology of this filter and depending on the mode being used. If a parallel component values are shown in the typical host communication mode is not being used, connection diagrams. Care should be taken when GPIO[11:0] must be terminated or driven as these laying out the filter circuitry to minimize trace pins will come up as high impedance inputs and lengths and to avoid any close routing of high will be prone to oscillation if they are left floating. frequency signals. Any noise coupled on to the The specific termination requirements may vary filter circuit will be directly coupled into the PLL, since the state of some of the GPIO pins will which could affect performance. determine the communication mode at the rising edge of reset (please see section 6 for more 24 DS262F2 CS4923/4/5/6/7/8/9 +3.3V Supply (+3.3VD) NOTE: A capacitor pair (1 u F and 0.1 uF) must be supplied for each power pin. NOTE: +3.3VA is simply +3.3VD after fil tering through the ferrite bead. Pin 32 must be referenced to +3.3VA FERRITE BEAD +3.3VA + 1 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF + 47 uF +3.3VD +3.3VD Resistor Pack 10k 4.70K 4.70K 4.70K 4.70K 10k 10k 10k NOTE: Only AUDATA0 connection applies for the CS4929 23 12 34 1 37 VD3 VD2 VD1 VA DD 33 MCLK 44 38 DC 33 SCLK 43 I 2 C I N T E R FAC E LRCLK 42 MICROCONTR OLLER 20 19 INTREQ DAC (S) SCDIO AU DATA 0 41 6 SCDIN AU DATA 1 40 18 CS AU DATA 2 39 7 SCCLK 36 RESET C M P DAT 27 28 CS4923/4/5/6/7/8/9 CMPCLK 29 DIR or CMPREQ AD C [S] S DATA N 22 4 WR__GPIO10 SCLKN 25 5 RD__GPIO11 OPT_TX SLRCLKN 26 21 GPIO8 XMT958 3 8 GPIO7 9 GPIO6 33 30 10 GPIO5 CLKIN OSCILLATOR 11 GPIO4 14 GPIO3 CLKSEL 31 15 GPIO2 10k 32 16 F LT 2 +3.3VA DGND1 DGND2 DGND3 GPIO1 AGND 17 GPIO0 F LT 1 33 E M A D _ G P IO [8:0] 13 24 35 + 2.2 uF 2 0.22 uF 10k Figure 13. I2C Control DS262F2 25 CS4923/4/5/6/7/8/9 +3.3V Supply (+3.3VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +3.3VA is simply +3.3VD after filt ering through the ferrite bead. Pin 32 must be referenced to +3.3VA FERRITE BEAD +3.3VA + 1 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF + 47 uF +3.3VD +3.3VD Resistor Pack 10k 4.70K 4.70K 4.70K 4.70K 10 k 10 k 10k 10k NOTE: Only AUDATA0 connection applies for the CS4929 23 12 34 1 37 VD3 VD2 VD1 VA DD 33 MCLK 44 38 DC 33 SCLK 43 42 I2C INTERFACE SYSTEM 20 I N T R E Q _ _ A B O OT LRCLK DAC s 19 SCDIO AU DATA 0 41 6 M I C RO 18 SCDIN CS AU DATA 1 40 AU DATA 2 39 7 SCCLK CONTROL LER 36 RESET C M P DAT 27 28 CMPCLK 29 DIR or CS4923/4/5/6/7/8/9 CMPREQ ADCs EXTERNAL ROM 4 WR__GPIO10 S DATA N 22 SCLKN 25 /CE 5 RD__EMOE OPT_TX SLRCLKN 26 /O E 21 EXTMEM 3 XMT958 8 EMAD7 9 EMAD6 33 30 OCTAL F/ F OCTAL F/ F 10 EMAD5 CLKIN OSCILLATOR 11 EMAD4 14 EMAD3 CLKSEL 31 A[15:8] Q[7:0] Q[7:0] 15 EMAD2 10k 32 16 F LT 2 +3.3VA DGND1 DGND2 DGND3 EMAD1 AGND D[7:0] D[7:0] 17 33 EMAD0 F LT 1 EMAD[7:0] A[7:0] 13 24 35 + 2.2 uF 2 0.22 uF D[7:0] 10k Figure 14. I2C Control with External Memory 26 DS262F2 CS4923/4/5/6/7/8/9 +3.3V Supply (+3.3VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +3.3VA is simply +3.3VD after filt ering through the ferrite bead. Pin 32 must be referenced to +3.3VA FERRITE BEAD +3.3VA + 1 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF + 47 uF +3.3VD +3.3VD Resistor Pack 10k 4.70K 4.70K 4.70K 10 k 10k NOTE: Only AUDATA0 connection applies for the CS4929 23 12 34 37 1 VD3 VD2 VD1 VA DD 33 MCLK 44 38 DC 33 SCLK 43 MICROCONTR OLLER 42 S P I I N T E R FAC E LRCLK 20 19 INTREQ DAC s SCDOUT AU DATA 0 41 6 SCDIN AU DATA 1 40 18 CS AU DATA 2 39 7 SCCLK 36 RESET C M P DAT 27 28 CS4923/4/5/6/7/8/9 CMPCLK 29 DIR or CMPREQ ADCs S DATA N 22 5 RD__GPIO11 SCLKN 25 4 WR__GPIO10 OPT_TX SLRCLKN 26 21 GPIO8 XMT958 3 8 GPIO7 9 GPIO6 33 30 10 GPIO5 CLKIN OSCILLATOR 11 GPIO4 14 GPIO3 CLKSEL 31 15 GPIO2 10k 32 16 F LT 2 +3.3VA DGND1 DGND2 DGND3 GPIO1 AGND 17 GPIO0 F LT 1 33 E M A D _ G P IO [8:0] 13 24 35 + 2.2 uF 2 0.22 uF 10k Figure 15. SPI Control DS262F2 27 CS4923/4/5/6/7/8/9 +3.3V Supply (+3.3VD) NOTE: A capacitor pair (1 u F and 0.1 uF) must be supplied for each power pin. NOTE: +3.3VA is simply +3.3VD after fil tering through the ferrite bead. Pin 32 must be referenced to +3.3VA FERRITE BEAD +3.3VA + 1 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF + 47 uF +3.3VD +3.3VD Resistor Pack 10k 4.70K 4.70K 4.70K 10 k 10k 10k NOTE: Only AUDATA0 connection applies for the CS492 23 12 34 1 37 VD3 VD2 VD1 VA DD 33 MCLK 44 38 DC 33 SCLK 43 42 SYSTEM S P I I N T E R FAC E LRCLK 20 19 I N T R E Q _ _ A B O OT DAC s SCDOUT AU DATA 0 41 6 M I C RO 18 SCDIN CS AU DATA 1 40 AU DATA 2 39 7 SCCLK CONTROL LER 36 RESET C M P DAT 27 28 CMPCLK 29 DIR or CS4923/4/5/6/7/8/9 CMPREQ ADCs EXTERNAL S DATA N 22 ROM 5 RD__EMOE SCLKN 25 4 WR__GPIO10 OPT_TX /CE SLRCLKN 26 /O E 21 EXTMEM 3 XMT958 8 EMAD7 9 EMAD6 33 30 OCTAL F/ F OCTAL F/ F 10 EMAD5 CLKIN OSCILLATOR 11 EMAD4 14 EMAD3 CLKSEL 31 A[15:8] Q[7:0] Q[7:0] 15 EMAD2 10k 16 F LT 2 32 +3.3VA DGND1 DGND2 DGND3 EMAD1 AGND D[7:0] D[7:0] 17 33 EMAD0 F LT 1 EMAD[7:0] A[7:0] 13 24 35 + 2.2 uF 2 0.22 uF D[7:0] 10k Figure 16. SPI Control with External Memory 28 DS262F2 CS4923/4/5/6/7/8/9 +3.3V Supply (+3.3VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +3.3VA is simply +3.3VD after filt ering through the ferrite bead. Pin 32 must be referenced to +3.3VA FERRITE BEAD +3.3VA + 1 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF + 47 uF +3.3VD +3.3VD Resistor Pack 10k 4.70K 4.70K 4.70K 10k 10k 10k NOTE: Only AUDATA0 connection applies for the CS4929 23 12 34 1 37 VD3 VD2 VD1 33 VA DD MCLK 44 38 DC 33 SCLK 43 MICROCONTR OLLER INT INTERFACE LRCLK 42 20 8 INTREQ DAC s DATA 7 AU DATA 0 41 9 DATA 6 AU DATA 1 40 10 DATA 5 AU DATA 2 39 11 DATA 4 14 DATA 3 C M P DAT 27 15 DATA 2 28 16 DATA 1 CMPCLK 29 DIR or DATA[7:0] 17 DATA 0 CMPREQ ADCs CS4923/4/5/6/7/8/9 21 GPIO8 S DATA N 22 SCLKN 25 OPT_TX 5 RD SLRCLKN 26 4 WR XMT958 3 6 A1 7 A0 33 30 18 CS CLKIN OSCILLATOR 36 RESET CLKSEL 31 10k 32 19 F LT 2 +3.3VA DGND1 DGND2 DGND3 PSEL_GPIO9 AGND F LT 1 33 10k 13 24 35 + 2.2 uF 2 0.22 uF Figure 17. Intel Parallel Control Mode DS262F2 29 CS4923/4/5/6/7/8/9 +3.3V Supply (+3.3VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +3.3VA is simply +3.3VD after filt ering through the ferrite bead. Pin 32 must be referenced to +3.3VA FERRITE BEAD +3.3VA + 1 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF + 47 uF +3.3VD +3.3VD Resistor Pack 10k 4.70K 4.70K 4.70K 10k 10k 10k 10k 23 NOTE: Only AUDATA0 connection applies for the CS4929 12 34 1 37 VD3 VD2 VD1 33 VA DD MCLK 44 38 DC 33 SCLK 43 MICROCONTR OLLER LRCLK 42 20 M OT I N T E R FAC E 8 INTREQ DAC s DATA 7 AU DATA 0 41 9 DATA 6 AU DATA 1 40 10 DATA 5 AU DATA 2 39 11 DATA 4 14 DATA 3 C M P DAT 27 15 DATA 2 28 16 DATA 1 CMPCLK 29 DIR or DATA[7:0] 17 DATA 0 CMPREQ ADCs CS4923/4/5/6/7/8/9 21 GPIO8 S DATA N 22 SCLKN 25 OPT_TX 19 PSEL_GPIO9 SLRCLKN 26 5 R/W__RD 4 DS__WR XMT958 3 33 6 30 7 A1 CLKIN OSCILLATOR A0 18 CS CLKSEL 31 10k 32 36 F LT 2 +3.3VA DGND1 DGND2 DGND3 RESET AGND F LT 1 33 13 24 35 + 2.2 uF 2 0.22 uF Figure 18. Motorola Parallel Control Mode 30 DS262F2 CS4923/4/5/6/7/8/9 4. POWER and a 1uF capacitor as close as physically possible The CS492X requires a 3.3V digital power supply to each power pin. The 0.1uF capacitor should be for the digital logic within the DSP and a 3.3V closest to the device (typically 5mm or closer). analog power supply for the internal PLL. There 4.2 Analog Power Conditioning are three digital power pins, VD1, VD2 and VD3, In order to obtain the best performance from the along with three digital grounds, DGND1, DGND2 CS4923/4/5/6/7/8/9’s internal PLL, the analog and DGND3. There is one analog power pin, VA power supply (VA) must be as clean as possible. A and one analog ground, AGND. The DSP will ferrite bead should be used to filter the 3.3V power perform at its best when noise has been eliminated supply for the analog portion of the CS492X. This from the power supply. The recommendations power scheme is shown in the typical connection given below for decoupling and power diagrams. conditioning of the CS492X will help to ensure reliable performance. 4.3 Pads 4.1 Decoupling Revision D and all subsequent revisions incorporate 5V tolerant pads. This means that while It is good practice to decouple noise from the the CS492X power supplies require 3.3 volts, 5 volt power supply by placing capacitors directly signals can be applied to the inputs without between the power and ground of the CS492X. damaging the part. Each pair of power pins (VD1/DGND, VD2/DGND, VD3/DGND, VA/AGND) should The I/O pads for Revision B of the CS4923/4/5/6 have its own decoupling capacitors. The are not 5 volt tolerant. Input levels for revision B of recommended procedure is to place both a 0.1uF the CS4923/4/5/6 should be no greater than 3.3 DS262F2 31 CS4923/4/5/6/7/8/9 5. CLOCKING The PLL reference clock has three possible sources Revision D of the CS4923/4/5/6/7/8/9 also that are routed through a multiplexer controlled by incorporates a programmable phase locked loop the DSP: SCLKN2, SCLKN1, and CLKIN. (PLL) clock synthesizer. The PLL takes an input Typically, in audio/video environments like set-top reference clock and produces all the internal clocks boxes, the CLKIN pin is connected to 27 MHz. In required to run the internal DSP and to provide other scenarios such as an A/V receiver design, the master mode timing to the audio input/output PLL can be clocked through the CLKIN pin with peripherals. The clock manager also includes a even multiples of the desired sampling rate or with 33-bit system time clock (STC) to support audio an already available clock source. CLKIN is and video synchronization in broadcast typically a multiple of a standard sampling applications. frequency in this scenario (e.g. 11.2896 MHz). The PLL can be internally bypassed by connecting The clock manager is controlled by the DSP the CLKSEL pin to VD. This connection application software. Please refer to the Hardware multiplexes the CLKIN pin directly to the DSP User’s Guide for the CS4923/4/5/6/7/8/9 (AN115) clock. Care should be taken to note the minimum and all relevant application code user’s guides for CLKIN requirements when bypassing the PLL. information on supported CLKIN frequencies and how to set up and control the internal PLL. 32 DS262F2 CS4923/4/5/6/7/8/9 6. CONTROL CS4926 or CS4928 for DTS decode. An image of Control of the CS4923/4/5/6/7/8/9 can be the DTS tables is available from the factory. accomplished through one of four methods. The Below is a brief discussion of each of the CS492X supports I2C and SPI serial communication modes available for the communication. In addition the CS492X supports CS4923/4/5/6/7/8/9. For a complete description of both a Motorola and Intel byte wide parallel host these communication modes along with flow control mode. Only one of the four communication charts, pseudocode and restrictions, please consult modes can be selected for control. The states of the the CS4923/4/5/6/7/8/9 Hardware User’s Guide. A RD, WR, and PSEL pins at the rising edge of complete understanding of the decoder and its RESET determine the interface type as shown in operation can not be accomplished without table 2. consulting the CS4923/4/5/6/7/8/9 Hardware User’s Guide and the application code user’s guides. RD WR PSEL Host Interface Mode (Pin 5) (Pin 4) (Pin 19) 6.1 Boot and Control Mode Overview 1 1 1 8-bit Motorola 1 1 0 8-bit Intel Regardless of which communication mode is used, 0 1 X the CS4923/4/5/6/7/8/9 must be booted and loaded Serial I2C 1 0 X Serial SPI with code at run time. The general sequence from a Table 2. Host Modes hardware perspective is as follows: 5) RESET Low Whichever host communication mode is used, host 6) Set Communication Configuration Pins control of the CS4923/4/5/6/7/8/9 is handled through the application software running on the 7) RESET High DSP. Configuration and control of the CS492X 8) Download Code decoder and its peripherals are indirectly executed 9) Configure Hardware through a messaging protocol supported by the downloaded application code. In other words 10) Configure Application Code successful communication can only be 11) Kickstart the Decoder accomplished by following the low level hardware The host has three options for code download: communication format and high level messaging protocol. The specifications of the messaging • Parallel Download through the parallel host in- protocol can be found in any of the application terface code user’s guides. • Serial download through either the SPI or I2C It should be noted that when using the CS4926 or interface CS4928 for DTS decoding, an external memory • Autoboot with external memory when using a interface must be used for DTS tables that are serial communication mode. required for decoding. (see section 6.5 for Once again the CS4923/4/5/6/7/8/9 Hardware information on external memory). The external User’s Guide should be consulted for a complete memory interface and the parallel interface modes description of the boot and download procedure can not be used together. For this reason the system including the necessary communication designer must use one of the serial communication handshaking. Hardware configuration is also modes with external memory if designing with the DS262F2 33 CS4923/4/5/6/7/8/9 covered in the CS4923/4/5/6/7/8/9 Hardware each signal on the CS4923/4/5/6/7/8/9. RD and User’s Guide. Application configuration is WR have no effect when CS is held high. described in the application code user’s guide for When the DSP writes a byte to the HOSTMSG the code being used. register, the HOUTRDY bit in the CONTROL 6.2 Parallel Host Interface register is set to indicate that there is data to be read. To initiate a read cycle the host should drive The byte wide parallel host interface of the CS low. When CS is low, RD becomes the output CS492X supports application code download, enable for DATA[7:0]. When CS and RD are low, communication for hardware and application the contents of register address A[1:0] are driven configuration, compressed data input, and PCM on the DATA[7:0] bus. The address A[1:0] must be data input. When using either Intel or Motorola valid a minimum time before either CS or RD goes modes, the parallel interface is implemented using low. The HOUTRDY bit of the CONTROL four 8-bit internal registers which are selectable register is cleared after the host reads from the using inputs A1 and A0 as shown in table 3. Table HOSTMSG register. 5 shows the individual registers and their bit mapping. Driving both CS and WR low begins an 8-bit write cycle. The address A[1:0] must be valid a In either the Intel or Motorola mode the INTREQ minimum time before either CS or WR goes low. pin can be used to interrupt the host when the DSP On the first rising edge of CS or WR, the write has unsolicited outgoing messages to be read. For cycle ends and DATA[7:0] are latched internally specific details on the behavior of INTREQ in one by the CS492X. Data must be held sufficiently to of the parallel modes, please see the satisfy the hold time as given in the timing section. CS4923/4/5/6/7/8/9 Hardware User’s Guide. The HINBSY bit is set when the host writes the HOSTMSG register. This bit is cleared when the A1 A0 Register Name Register Function byte in the HOSTMSG register is read by the DSP. (Pin 6) (Pin 7) During RESET low, all control signals have no 1 1 CMPDATA 8-bit compressed data to input unit effect and DATA[7:0] are high impedance. (write only) 1 0 PCMDATA 8-bit linear PCM data Pin Name Pin Description Pin Number to input unit (write CS Chip Select 18 only) RD Output Enable 5 0 1 CONTROL Multi-bit control regis- WR Write Enable 4 ter for setup and A1 Register Address 1 6 handshaking (R/W) A0 Register Address 0 7 0 0 HOSTMSG 8-bit control pipe INTREQ Interrupt Request 20 message register DATA7 Data Bit 7 8 (R/W) DATA6 Data Bit 6 9 Table 3. Host Memory Map DATA5 Data Bit 5 10 DATA4 Data Bit 4 11 6.2.1 Intel Parallel Host Mode DATA3 Data Bit 3 14 DATA2 Data Bit 2 15 Intel parallel host mode is accomplished with CS, DATA1 Data Bit 1 16 RD, WR, A[1:0], and DATA[7:0]. Table 4 shows DATA0 Data Bit 0 17 the pin name, pin description and pin number of Table 4. Intel Parallel Host Mode Pin Assignments 34 DS262F2 CS4923/4/5/6/7/8/9 Host Message (HOSTMSG) Register, A[1:0] = 00b 7 6 5 4 3 2 1 0 HOSTMSG7 HOSTMSG6 HOSTMSG5 HOSTMSG4 HOSTMSG3 HOSTMSG2 HOSTMSG1 HOSTMSG0 HOSTMSG7–0 Host data to and from the DSP. A read or write of this register operates handshake bits between the internal DSP and the external host. This register typically passes multibyte messages car- rying microcode, control, and configuration data. HOSTMSG is physically implemented as two independent registers for input and output. (Read and write) Host Control (CONTROL) Register, A[1:0] = 01b 7 6 5 4 3 2 1 0 Reserved CMPRST PCMRST MFC MFB HINBSY HOUTRDY Reserved Reserved Always write a 0 for future compatibility. CMPRST When set, initializes the CMPDATA compressed data input channel. Writing a one to this bit holds the port in reset. Writing zero enables the port. This bit must be low for normal operation. (Write only) PCMRST When set, initializes the linear PCM input channel. This bit is toggled to indicate the first sample of the left channel for a PCM stream. Writing a one to this bit holds the port in reset. Writing zero enables the port. This bit must be low for normal operation. (Write only) MFC When high, indicates that the PCMDATA input buffer is almost full. The input buffer threshold level is application code dependent. (Read only) MFB When high, indicates that the CMPDATA input buffer is almost full. The input buffer threshold level is application code dependent. (Read only) HINBSY Set when the host writes to HOSTMSG. Cleared when the DSP reads data from the HOSTMSG register. The host reads this bit to determine if the last host byte written has been read by the DSP. (Read only) HOUTRDY Set when the DSP writes to the HOSTMSG register. Cleared when the host reads data from the HOSTMSG register. The DSP reads this bit to determine if the last DSP output byte has been read by the host. (Read only) Reserved Always write a 0 for future compatibility. PCM Data Input (PCMDATA) Register, A[1:0] = 10b 7 6 5 4 3 2 1 0 PCMDATA7 PCMDATA6 PCMDATA5 PCMDATA4 PCMDATA3 PCMDATA2 PCMDATA1 PCMDATA0 PCMDATA7–0 The host writes PCM data to the DSP input buffer at this address. (Write only) Compressed Data Input (CMPDATA) Register, A[1:0] = 11b 7 6 5 4 3 2 1 0 CMPDATA7 CMPDATA6 CMPDATA5 CMPDATA4 CMPDATA3 CMPDATA2 CMPDATA1 CMPDATA0 CMPDATA7–0 The host writes compressed data to the DSP input buffer at this address. (Write only) Table 5. Parallel Input/Output Registers DS262F2 35 CS4923/4/5/6/7/8/9 6.2.2 Motorola Parallel Host Mode Pin Name Pin Description Pin Number CS Chip Select 18 Motorola parallel host mode is accomplished with DS Data Strobe 4 CS, DS, R/W, A[1:0], and DATA[7:0]. Table 6 R/W Read or Write Enable 5 shows the pin name, pin description and pin A1 Register Address 1 6 number of each signal on the CS4923/4/5/6/7/8/9. A0 Register Address 0 7 In Motorola host interface mode, the host interface INTREQ Interrupt Request 20 pins act as an active-low chip select, CS, an active- DATA7 Data Bit 7 8 low data strobe, DS, and a R/W control signal. DATA6 Data Bit 6 9 DATA5 Data Bit 5 10 Internally to the CS492X, DS and CS are logically DATA4 Data Bit 4 11 ANDED. Therefore, in some cases, DS and CS can DATA3 Data Bit 3 14 be externally tied together with a common active- DATA2 Data Bit 2 15 low strobe. Otherwise, in long decoder delay DATA1 Data Bit 1 16 scenarios, read or write cycles can be terminated DATA0 Data Bit 0 17 earlier by connecting the microprocessor active- Table 6. Motorola Parallel Host Mode Pin Assignments low data-strobe signal to the CS492X DS and a delayed final active-low chip select independently 6.3 SPI Serial Host Interface to the CS pin. For SPI communications, the CS4923/4/5/6/7/8/9 always acts as a slave. Serial SPI communication When the DSP writes a byte to the HOSTMSG with the CS4923/4/5/6/7/8/9 is accomplished with register, the HOUTRDY bit in the CONTROL 5 communication lines: CS, SCCLK, SCDIN, register is set to indicate that there is data to be SCDOUT and INTREQ. Table 7 shows the pin read. During read cycles, DATA[7:0] are driven name, pin description and pin number of each when R/W is high and DS and CS are both low. signal on the CS4923/4/5/6/7/8/9. CS is an active DATA[7:0] are released with the earliest of CS or low chip select and must be held low for writes to DS going high. The HOUTRDY bit of the and reads from the part. SCCLK is an input to the CONTROL register is cleared after the host reads CS492X that clocks data in and out of the device on from the HOSTMSG register. its rising edge. SCDIN is the data input and should Write cycles occur with R/W low followed by DS be valid on the rising edge of SCCLK. SCDOUT is and CS both going low. The A[1:0] address pins the data output and will be valid on the rising edge select the specific address of the register to be of SCCLK. INTREQ is an open drain, active-low written and DATA[7:0] carry the data to be written. interrupt request signal that is driven low by the For write cycles, the first of CS and DS going high CS492X when there is data to be read out. latches data. Data must be held sufficiently to satisfy the hold time as given in the timing section. Pin Name Pin Description Pin Number The HINBSY is set when the host writes the CS Chip Select 18 HOSTMSG register. This bit is cleared when the SCDIN Serial Data Input 6 SCCLK Serial Control Clock 7 byte in the HOSTMSG is internally read by the SCDOUT Serial Data Output 19 DSP. INTREQ Interrupt Request 20 Table 7. SPI Serial Mode Pin Assignments 36 DS262F2 CS4923/4/5/6/7/8/9 6.3.1 SPI Write The host initiates an SPI read by driving CS low, followed by a 7-bit address and the read/write bit When writing to the device in SPI, the same set high to indicate a read. The CS492X internal 7- protocol can be used for sending a byte, a word or bit address is initially assigned to 000 0000b an entire download image as long as transfers occur following a reset. The 7-bit address sent to the on byte boundaries. Figure 19 illustrates the CS492X must match its internal address or the relative timing necessary for a three byte transfer to incoming data will be ignored. Address checking the CS492X. The host initiates an SPI write by can be disabled or the actual address can be driving CS low, followed by a 7-bit address and the changed if desired. Address checking read/write bit set low to indicate a write. The configuration is documented in the hardware CS4923/4/5/6/7/8/9 internal 7-bit address is configuration section of the CS4923/4/5/6/7/8/9 initially assigned to 000 0000b following a reset. Hardware User’s guide. The 7-bit address sent to the CS492X must match its internal address or the incoming data will be After the address byte the host should clock data ignored. Address checking can be changed (either out of the device one byte at a time until INTREQ disabled or an actual address change) if desired. is no longer low. The host shifts data using the Address checking configuration is documented in rising edge of SCCLK. The data is valid on the the hardware configuration section of the rising edge of SCCLK and transitions occur on the CS4923/4/5/6/7/8/9 Hardware User’s guide. falling edge. In SPI mode, the INTREQ pin is deasserted immediately following the rising edge Data should be shifted into the CS492X most of the second-to-last data bit of the current byte significant bit first with data being valid at the being transferred if there is no more data to be read. rising edge of SCCLK. It should be noted that data The INTREQ pin is guaranteed to stay deasserted is internally transferred to the DSP on the falling (high) until the rising edge of SCCLK for the last edge of the eighth SCCLK after the eighth data bit data bit. of a byte. For this reason SCCLK must transition from high to low on the last bit of each byte or a If there is more data to be read from the DSP before loss of data will occur. If this final transfer of the rising edge of SCCLK for the second-to-last SCCLK does not occur the final byte will be lost data bit, then INTREQ remains asserted low. and successful communication will not be possible. Immediately following the falling edge of SCCLK for the last data bit of the current byte, the next data 6.3.2 SPI Read byte loads into the internal serial shift register. The The CS4923/4/5/6/7/8/9 will always indicate that it host should continue to read this new byte. It is has data to be read by asserting the INTREQ line important to note that once the data is in the shift low. The host must recognize the request and start register, clocks on the SCCLK line shift the data a read transaction with the CS492X. The same bits out of the shift register as long as CS is low. protocol will be used whether reading a byte or For a thorough look at SPI communication and multiple bytes. Figure 19 also illustrates the critical additional comments on INTREQ behavior relative timing of a three byte SPI read. reference the CS4923/4/5/6/7/8/9 Hardware User’s Guide. DS262F2 37 38 SCCLK SCDIN AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CS SPI Write Functional Timing SCCLK SCDIN AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W SCDOUT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CS INTREQ SPI Read Functional Timing Note 1 Note 2 Notes: 1. INTREQ is guaranteed to stay low until the rising edge of SCCLK for the second to last bit of the last byte to be transferred out of the CS4923/4/5/6/7/8/9 2. INTREQ is guaranteed to stay high until the next rising edge of SCCLK at which point it may go low again if there is new data to be read. The condition of INTREQ going low at this point should be treated as a new read condition and a new start condition followed by an address byte should be sent CS4923/4/5/6/7/8/9 Figure 19. SPI Timing DS262F2 CS4923/4/5/6/7/8/9 6.4 I2C Serial Host Interface the actual address can be changed if desired. For I2C communications the CS4923/4/5/6/7/8/9 Address checking configuration is documented in always acts as a slave. Serial I2C communication the hardware configuration section of the with the CS4923/4/5/6/7/8/9 is accomplished with CS4923/4/5/6/7/8/9 Hardware User’s guide. After 3 communication lines: SCCLK, SCDIO and the address byte the host should then clock an INTREQ. Table 8 shows the mnemonic, pin name, acknowledge (ACK) from the part. During a write, and pin number of each signal on the an ACK is defined as SCDIO being driven low by CS4923/4/5/6/7/8/9. SCCLK is an input to the the CS492X for one SCCLK period after each byte. CS492X that clocks data in and out of the device on Data should be shifted into the CS492X most its rising edge. It should be noted that the timing significant byte first with data being valid at the rising specifications for SCCLK are more stringent than edge of SCCLK. The host should then clock out the certain I2C requirements so care should be taken acknowledge (ACK bit) bit from the CS492X. After that the rise and fall specifications for SCCLK are the last byte to be sent is acknowledged, the host met as stated in the timing portion of this data sheet. should send an I2C stop condition, which is defined as SCDIO is a bidirectional data line whose data must the rising edge of SCDIO while SCCLK is held high. be valid on the rising edge of SCCLK. INTREQ is If the CS492X fails to acknowledge a byte, the host an open drain, active-low request signal that is should re-transmit the same byte. If the CS492X driven low by the CS492X when there is data to be does not acknowledge back to back bytes, then the read out. host should reset the part. Pin Name Pin Description Pin Number 6.4.2 I2C Read SCCLK Serial Control Clock 7 SCDIO Serial Data Input and 19 The CS4923/4/5/6/7/8/9 will always indicate that it Output has data to be read by asserting the INTREQ line INTREQ Interrupt Request 20 low. The host must recognize the request and start a Table 8. I2C Serial Mode Pin Assignments read transaction with the CS492X. The same protocol will be used whether reading a byte or 6.4.1 I2C Write multiple bytes. Figure 20 also illustrates the relative When writing to the device in I2C, the same timing of a three byte I2C read. protocol can be used for sending a byte, a word or The host initiates a read with an I2C start condition an entire download image as long as transfers occur followed by a 7-bit address and the read/write bit set on byte boundaries. Figure 20 illustrates the high for a read. The start condition is defined as the relative timing necessary for a three byte transfer to SCDIO falling with SCCLK held high. The CS492X the CS492X. The host initiates a transfer with an internal 7-bit address is initially assigned to 000 I2C start condition followed by a 7-bit address and 0000b following a reset. The 7-bit address sent to the the read/write bit set low to indicate a write. The CS492X must match its internal address or the start condition is defined as the SCDIO falling with incoming data will be ignored. Address checking SCCLK held high. The CS492X internal 7-bit can be disabled or the actual address can be changed address is initially assigned to 000 0000b following if desired. Address checking configuration is a reset. The 7-bit address sent to the CS492X must documented in the hardware configuration section match its internal address or the incoming data will of the CS4923/4/5/6/7/8/9 Hardware User’s guide. be ignored. Address checking can be disabled or DS262F2 39 40 I2C Start I2C Stop SCCLK SCDIO AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK I2C Write Functional Timing I2C Start I2C Stop SCCLK SCDIO AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 NACK INTREQ Note 1 Note 2 Note 3 Note 5 Note 4 I2C Read Functional Timing Notes: 1. The ACK for the address byte is driven by the CS4923/4/5/6/7/8/9. 2. The ACKs for the data bytes being read from the CS4923/4/5/6/7/8/9 should be driven by the host. 3. INTREQ is guaranteed to stay low until the rising edge of SCCLK for last bit of the last byte to be transferred out of the CS4923/4/5/6/7/8/9 4. A NOACK should be sent by the host after the last byte read to indicate the end of the read cycle. CS4923/4/5/6/7/8/9 5. INTREQ is guaranteed to stay high until the next rising edge of SCCLK (for the ACK/NACK bit) at which point it may go low again if there is new data to be read. The condition of INTREQ going low at this point should be treated as a new read condition and a new start condition followed by an address byte should be sent. Figure 20. I2C Timing DS262F2 CS4923/4/5/6/7/8/9 Following the address byte the host must clock out The external memory interface is implemented on an acknowledge from the part. the CS4923/4/5/6/7/8/9 with the following signals: After the address byte, the host should clock out data EMAD[7:0], EXTMEM and EMOE. Table 9 shows from the device one byte at a time until INTREQ is the pin name, pin description and pin number of each no longer low. The host shifts data using the rising signal on the CS4923/4/5/6/7/8/9. EMAD[7:0] serve edge of SCCLK. The data is valid on the rising edge as a multiplexed address and data bus. EMOE is an of SCCLK and transitions on the falling edge. After active-low external-memory data output enable as each byte the host must send an acknowledge (ACK) well as the address latch strobe. EXTMEM serves as to the CS492X. While reading from the CS492X, an the active low chip select output. Figure 21 illustrates acknowledge is defined as SCDIO being driven low one possible external memory architecture for the by the host for one SCCLK period after each byte. In CS4923/4/5/6/7/8/9. Figure 22 shows the functional I2C mode, the INTREQ pin is deasserted timing of a run-time memory access . immediately following the rising edge of the last Pin data bit of the current byte being transferred if there Pin Name Pin Description Number is no more data to be read. The INTREQ pin is /EMOE * External Memory Output 5 guaranteed to stay deasserted (high) until the rising Enable & Address Latch edge of SCCLK for the acknowledge bit. Strobe /EMWR * External Memory Write 4 For a more thorough look at I2C communication Strobe and critical additional information on INTREQ /EXTMEM External Memory Select 21 behavior reference the CS4923/4/5/6/7/8/9 EMAD7 Address and Data Bit 7 8 EMAD6 Address and Data Bit 6 9 Hardware User’s Guide. EMAD5 Address and Data Bit 5 10 6.5 External Memory EMAD4 Address and Data Bit 4 11 EMAD3 Address and Data Bit 3 14 If using one of the serial modes, i.e. SPI or I2C, the EMAD2 Address and Data Bit 2 15 system designer has the option of using external EMAD1 Address and Data Bit 1 16 memory. The external memory interface is not EMAD0 Address and Data Bit 0 17 compatible with the parallel modes since there are * - These pins must be configured appropriately to select a shared pins that are needed by each mode. If using serial host communication mode for the CS4923/4/5/6/7/8/9 at the rising edge of RESET the CS4926 or CS4928 for DTS decode, external memory is required for external DTS tables. Table 9. Memory Interface Pins The external memory interface was designed The external memory address is capable of addressing primarily for two purposes: 1) Autoboot and/or 2) between 64 kilobytes and 16 megabytes through a 16 real time external data access. The hardware to 24 bit addressing scheme. The address comes from implementation for either mode can be the same but the DSP writing two or three initial bytes of address the ROM access time requirements may differ. The consecutively on EMAD[7:0]. Each byte of address is CS4923/4/5/6/7/8/9 Hardware User’s Guide should externally latched with the rising edge of EMOE while be referenced for more information including EXTMEM is high. After the 2 or 3-byte address is memory paging options to support both autoboot and latched externally, the CS4923/4/5/6/7/8/9 then drives real time access as well as ROM speed requirements. EXTMEM and EMOE low simultaneously to select the external memory. During this time the data is read by the CS492X. DS262F2 41 CS4923/4/5/6/7/8/9 3.3V 8 ADDR[7:0] EMAD[7:0] D Q ADDR[7:0] D A T A[7:0] 3.3V 8 BIT ADDR[15:8] D Q ADDR[15:8] '574 8 BIT CS4923/4/5/6/7/8/9 DFF '574 DFF EMOE OE 64K X 8 EXTMEM CS EMWR ROM 3.3V 3.3V Only one of R1 and R2 shou ld be stuffed. Only one of R3 and R4 shou ld be stuffed. The state of EMOE and EMWR at the rising edge of RESET will determine the R1 R3 serial mode that the part comes up in while using exter nal memory. Please see section 2, Serial Communication for R2 R4 more d etails. Figure 21. External Memory Interface EXTMEM EMOE EMAD7:0 MA15:8 MA7:0 Data7:0 Figure 22. Run-Time Memory Access 42 DS262F2 CS4923/4/5/6/7/8/9 Although the memory can use more address bits, ABOOT can be released following the rising edge typically only 16 bits of address space are used. For of RESET. During the automatic boot cycle, the this reason the memory example shown serial control port should remain idle. Figure 23 incorporates a 2 latch memory architecture. shows an autoboot functional timing example. The two latch external memory architecture is The autoboot cycle actually is a 24 bit, or three required for the CS4926 or CS4928 when using address byte cycle. It should be noted that for DTS. A three latch architecture can not be used autoboot, the most significant byte is always zero. with the CS4926 or CS4928 running DTS since the For this reason a two latch external memory run time memory access uses only 2 address cycles. configuration can be used for autoboot. The higher order address byte simply shifts out of the memory 6.5.1 External Memory and Autoboot latch and is discarded. If desired, a three latch To configure the CS4923/4/5/6/7/8/9 to interface could also be used with the automatically load its code from external memory, CS4923/4/5/7/9 but it is not necessary. the ABOOT signal should be driven low at the For more information about autoboot and for a rising edge of RESET. Once again this mode can thorough description of different external memory only be chosen if either SPI or I2C serial architectures, reference the CS4923/4/5/6/7/8/9 communication is being used. In serial control port Hardware User’s Guide. mode, holding the ABOOT pin low as the CS492X leaves the reset state enables an automatic boot. RESET ABOOT EXTMEM EMOE EMWR EMAD7:0 MA23:16 MA15:8 MA7:0 Data7:0 Figure 23. Autoboot Timing Diagram DS262F2 43 CS4923/4/5/6/7/8/9 7. DIGITAL INPUT & OUTPUT presented most significant bit first on the first The CS4923/4/5/6/7/8/9 supports a wide variety of SCLK after an LRCLK transition and is valid on data input and output mechanisms through various the rising edge of SCLK. For the left justified input and output ports. Hardware availability is format, the left subframe is presented when entirely dependent on whether the software LRCLK is high and the right subframe is presented application code being used supports the required when LRCLK is low. The left justified format can mode. This data sheet presents most of the modes also be programmed for data to be valid on the available with the CS4923/4/5/6/7/8/9 hardware. falling edge of SCLK. SCLK is required to run at a This does not mean that all of the modes are frequency of 48Fs or greater on the input ports. available with any particular piece of application Right Justified: Figure 26 shows the right justified code. Both the CS4923/4/5/6/7/8/9 Hardware format. The right justified format is similar to the User’s Guide and the application code user’s guide left justified format except the least significant bit for the particular code being used should be is right justified to be valid on the last transition of referenced to determine if a particular mode is SCLK before an LRCLK transition. Data is still supported. presented most significant bit first. For the right justified format, the left subframe is presented 7.1 Digital Audio Formats when LRCLK is high and the right subframe is This subsection will describe some common audio presented when LRCLK is low. The right justified formats that the CS4923/4/5/6/7/8/9 supports. It format can also be programmed for data being valid should be noted that the input ports use up to 24-bit on the falling edge of SCLK. SCLK is required to PCM resolution and 16-bit compressed data word run at a frequency of 48Fs or greater on the input lengths. The output port of the CS492X provides ports. up to 20-bit PCM resolution. Multi-Channel: Figure 27 shows the multi- I2S: Figure 24 shows the I2S format. For I2S, data is channel format. In this format up to 6 channels of presented most significant bit first, one SCLK audio are presented on one data line with 20 bits per delay after the transition of LRCLK and is valid on channel. Channels 0, 2, and 4 are presented while the rising edge of SCLK. For the I2S format, the left the LR-CLK is high and channels 1, 3, 5 are subframe is presented when LRCLK is low and the presented while the LRCLK is low. Data is valid on right subframe is presented when LRCLK is high. the rising edge of SCLK and is presented most SCLK is required to run at a frequency of 48Fs or significant bit first. greater on the input ports. Because each of the ports is fully configurable, Left Justified: Figure 25 shows the left justified there may be modes that can be supported which format with a rising edge SCCLK. Data is are not presented. 44 DS262F2 CS4923/4/5/6/7/8/9 LRCK Left Right SCLK SDATA MSB LSB MSB LSB Figure 24. I2S Format LRCK Left Right SCLK SDATA MSB LSB MSB LSB MSB Figure 25. Left Justified Format LRCLK Left Right SCLK SDATA LSB MSB LSB MSB LSB Figure 26. Right Justified LRCLK SCLK SDATA MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB M Clocks M Clocks M Clocks M Clocks M Clocks M Clocks Per Channel Per Channel Per Channel Per Channel Per Channel Per Channel Figure 27. Multi-Channel Format (M == 20) DS262F2 45 CS4923/4/5/6/7/8/9 7.2 Digital Audio Input Port The CDI can be configured to support I2S, left The digital audio input port, or DAI, is used for justified and right justified formats. The CDI can both compressed and PCM digital audio data input. also be programmed for slave clocks, where In addition this port supports a special clocking LRCLKN2 and SCLKN2 are inputs, or master mode in which a clock can be input to directly drive clocks, where LRCLKN2 and SCLKN2 are the internal 33 bit counter. Table 10 shows the pin outputs. In order for clocks to be mastered, the names, mnemonics and pin numbers associated internal PLL must be used. with the DAI. In addition the CDI can be configured for bursty compressed data input. Bursty audio delivery is a Pin Name Pin Description Pin Number special format in which only clock (CMPCLK) and SDATAN1 Serial Data In 22 data (CMPDAT) are used to deliver compressed SCLKN1 Serial Bit Clock 25 LRCLKN1 Frame Clock 26 data to the CS4923/4/5/6/7/8/9 (i.e. no frame clock or LRCLK). A third line, CMPREQ, is used to Table 10. Digital Audio Input Port request more data from the host. It is an indicator The DAI can be programmed to support I2S, left that the CS492X internal FIFO is low on data and justified and right justified data input. In addition can accept another burst. Typically this mode is the DAI can be programmed for slave clocks, used for compressed data delivery where where LRCLKN1 and SCLKN1 are inputs, or asynchronous data transfer occurs in the system, master clocks, where LRCLKN1 and SCLKN1 are i.e. in a system such as a set-top box or HDTV. outputs. In order for clocks to be master, the PCM data can not be presented in this mode since internal PLL must be used. data is interpreted as a continuous stream with no word boundaries. STCCLK2 can also be programmed to drive the internal 33 bit counter. This counter would 7.4 Parallel Digital Audio Data Input typically be driven by a 90kHz clock. The internal If using the Intel or Motorola Parallel host interface counter is used by certain application code for mode, the system designer can also choose to audio/video synchronization purposes. deliver data through the byte wide parallel port. 7.3 Compressed Data Input Port The compressed data input register receives bytes of data when the host interface writes to address The compressed data input port, or CDI, can be 11b (A1 and A0 are both high). The host interface used for both compressed and PCM data input. port also utilizes the CMPREQ pin and the MFB Table 11 shows the mnemonic, pin name and pin and MFC flags in the CONTROL register, which number of the pins associated with the CDI port on are configurable to supply a data request flag at the CS4923/4/5/6/7/8/9. different input buffer thresholds. CMPREQ acts as Pin Name Pin Description Pin Number an almost full flag. The CS4923/4/5/6/7/8/9 can SDATAN2 Serial Data In 27 safely receive different size blocks of data CMPDATA Compressed Data In depending on the level of the input buffer SCLKN2 Serial Bit Clock 28 threshold. The threshold level is programmable and CMPCLK the default level may differ between applications. LRCLKN2 Frame Clock 29 CMPREQ Data Request Out This mode reduces the polling burden associated Table 11. Compressed Data Input Port with hand-feeding the compressed data. 46 DS262F2 CS4923/4/5/6/7/8/9 In parallel host mode, the CS4923/4/5/6/7/8/9 can MCLK is the master clock and is firmware accept PCM data written through the byte-wide configurable to be either an input or an output. If host interface to address 10b (A1 high, A0 low). In MCLK is to be used as an output, the internal PLL this mode, there is a close connection between the must be used. As an output MCLK can be CS4923/4/5/6/7/8/9 application code and the host configured to provide a 128Fs, 256Fs or 512Fs processor that is delivering the PCM data. The clock, where Fs is the output sample rate. PCMRST bit of the CONTROL register provides SCLK is the bit clock used to clock data out on absolute software/hardware synchronization by AUDATA0, AUDATA1 and AUDATA2. LRCLK initializing the input channel to uniquely recognize is the data framing clock whose frequency is the first write to the byte-wide PCMDATA port. typically equal to the sampling frequency. Both Toggling PCMRST high and low informs the DSP LRCLK and SCLK can be configured as either that the next sample read from the PCMDATA port inputs (Slave mode) or outputs (Master mode). is the first sample of the left channel. In this When LRCLK and SCLK are configured as inputs, fashion, the CS492X can translate successive byte MCLK is a don’t care as an input. When LRCLK writes into a variable number of channels with a and SCLK are configured as outputs, they are variable PCM sample size. In the most simple case, derived from MCLK. Whether MCLK is the CS492X can receive stereo 8-bit PCM one byte configured as an input or an output, an internal at a time with the internal DSP assigning the first divider from the MCLK signal is used to produce 8-bit write (after PCMRST) to the left channel and LRCLK and SCLK. The ratios shown in table 13 the second 8-bit write to the right channel. For give the possible SCLK values for different MCLK 16-bit PCM, it assigns the first two 8-bit writes frequencies (all values in terms of the sampling (after PCMRST) to the left channel and the next frequency, Fs). two writes to the right channel. MCLK SCLK (Fs) 7.5 Digital Audio Output Port (Fs) 32 48 64 128 256 512 The Digital Audio Output port, or DAO, is the port 128 X X used for digital output from the DSP. Table 12 384** X X X shows the signals associated with the DAO. As 256 X X X X 512 X X X X X there are many modes that are firmware configurable on the DAO, please consult the ** For MCLK as an input only Hardware User’s Guide and the application code Table 13. MCLK/SCLK Master Mode Ratios user’s guides to determine which modes are AUDAT0 is configurable to provide six, four, or supported by the download code being used. two channels. AUDAT1 and AUDAT2 can both output two channels of data. Typically all three Pin Name Pin Description Pin Number AUDAT outputs are used in left justified, I2S or AUDAT2 Serial Data In 39 right justified modes. In this way all six channels of AUDAT1 Serial Data In 40 AUDAT0 Serial Data In 41 surround (Left, Center, Right, Left Surround, Right LRCLK Frame Clock 42 Surround and Subwoofer) are provided. SCLK Serial Bit Clock 43 Alternatively the multi-channel mode can be MCLK Master Clock 44 configured to provide single data line multi- XMT958 IEC60958 Transmitter 3 channel support. Please consult the Hardware Table 12. Digital Audio Output Port User’s Guide and the application code user’s DS262F2 47 CS4923/4/5/6/7/8/9 guides to determine which modes are supported by 7.5.1 IEC60958 Output the download code being used. The XMT958 output provides a CMOS level bi Serial digital audio data bit placement and sample phase encoded output. The XMT958 function can alignment is fully configurable in the be internally clocked from the PLL or from an CS4923/4/5/6/7/8/9 including left justified, right MCLK input if MCLK is 256Fs or 512Fs. All justified, delay bits or no delay bits, variable channel status information can be used when using sample word sizes, variable output channel count, software which supports this functionality. This and programmable output channel pin assignments output can be used for either 2 channel PCM output and clock edge polarity to integrate with most or compressed data output in accordance with digital audio interfaces. If a mode is needed which IEC61937. To be fully IEC60958 compliant this is not supported, please consult your Crystal output would need to be buffered through an Representative as to its availability. RS422 device or an optocoupler as its outputs are only CMOS. Please consult the CS4923/4/5/6/7/8/9 Hardware User’s Guide and an application code user’s guide to determine if this pin is supported by the download code being used. 48 DS262F2 CS4923/4/5/6/7/8/9 8. PIN DESCRIPTIONS VD1 DGND1 MCLK XMT958 SCLK WR,DS,EMWR,GPIO10 LRCLK RD,R/W,EMOE,GPIO11 AUDATA0 A1, SCDIN AUDATA1 A0, SCCLK AUDATA2 DATA7,EMAD7,GPIO7 6 5 4 3 2 1 44 43 42 41 40 DC 7 39 DATA6,EMAD6,GPIO6 8 38 DD DATA5,EMAD5,GPIO5 9 37 RESET 10 36 DATA4,EMAD4,GPIO4 AGND 11 35 CS4923-CL VD2 12 34 VA 44-pin PLCC DGND2 13 33 FILT1 14 Top View 32 DATA3,EMAD3,GPIO3 15 31 FILT2 DATA2,EMAD2,GPIO2 16 30 CLKSEL 17 29 DATA1,EMAD1,GPIO1 18 19 20 21 22 23 24 25 26 27 28 CLKIN DATA0,EMAD0,GPIO0 CMPREQ, LRCLKN2 CS CMPCLK, SCLKN2 SCDIO, SCDOUT,PSEL,GPIO9 CMPDAT, SDATAN2 ABOOT, INTREQ LRCLKN1 EXTMEM, GPIO8 SCLKN1, STCCLK2 SDATAN1 DGND3 VD3 VA—Analog Positive Supply: Pin 34 Analog positive supply for clock generator. Nominally +3.3 V. AGND—Analog Supply Ground: Pin 35 Analog ground for clock generator PLL. VD1, VD2, VD3—Digital Positive Supply: Pins 1, 12, 23 Digital positive supplies. Nominally +3.3 V. DGND1, DGND2, DGND3—Digital Supply Ground: Pins 2, 13, 24 Digital ground. FILT1—Phase-Locked Loop Filter: Pin 33 Connects to an external filter for the on-chip phase-locked loop. This pin does not meet Cirrus Logic’s ESD tolerance of 2000 V using the human body model. This pin will tolerate ESD of 1000 V using the human body model. DS262F2 49 CS4923/4/5/6/7/8/9 FILT2—Phase Locked Loop Filter: Pin 32 Connects to an external filter for the on-chip phase-locked loop. This pin does not meet Cirrus Logic’s ESD tolerance of 2000 V using the human body model. This pin will tolerate ESD of 1000 V using the human body model. CLKIN—Master Clock Input: Pin 30 CS4923/4/5/6/7/8/9 clock input. When in internal clock mode (CLKSEL == DGND), this input is connected to the internal PLL from which all internal clocks are derived. When in external clock mode (CLKSEL == VD), this input is connected to the DSP clock. INPUT CLKSEL—DSP Clock Select: Pin 31 This pin selects the clock mode of the CS4923/4/5/6/7/8/9. When CLKSEL is low, CLKIN is connected to the internal PLL from which all internal clocks are derived. When CLKSEL is high CLKIN is connected to the DSP clock. INPUT DATA7, EMAD7, GPIO7—Pin 8 DATA6, EMAD6, GPIO6—Pin 9 DATA5, EMAD5, GPIO5—Pin 10 DATA4, EMAD4, GPIO4—Pin 11 DATA3, EMAD3, GPIO3—Pin 14 DATA2, EMAD2, GPIO2—Pin 15 DATA1, EMAD1, GPIO1—Pin 16 DATA0, EMAD0, GPIO0—Pin 17 In parallel host mode, these pins provide a bidirectional data bus. If a serial host mode is selected, these pins can provide a multiplexed address and data bus for connecting an 8-bit external memory. Otherwise, in serial host mode, these pins can act as general-purpose input or output pins that can be individually configured and controlled by the DSP. BIDIRECTIONAL - Default: INPUT A0, SCCLK—Host Parallel Address Bit Zero or Serial Control Port Clock: Pin 7 In parallel host mode, this pin serves as one of two address input pins used to select one of four parallel registers. In serial host mode, this pin serves as the serial control clock signal, specifically as the SPI clock input or the I2C clock input. INPUT A1, SCDIN—Host Parallel Address Bit One or SPI Serial Control Data Input: Pin 6 In parallel host mode, this pin serves as one of two address input pins used to select one of four parallel registers. In SPI serial host mode, this pin serves as the data input. INPUT RD, R/W, EMOE, GPIO11—Host Parallel Output Enable or Host Parallel R/W or External Memory Output Enable or General Purpose Input & Output Number 11: Pin 5 In Intel parallel host mode, this pin serves as the active-low data bus enable input. In Motorola parallel host mode, this pin serves as the read-high/write-low control input signal. In serial host mode, this pin can serve as the external memory active-low data-enable output signal. Also in serial host mode, this pin can serve as a general purpose input or output bit. BIDIRECTIONAL - Default: INPUT 50 DS262F2 CS4923/4/5/6/7/8/9 WR, DS, EMWR, GPIO10—Host Write Strobe or Host Data Strobe or External Memory Write Enable or General Purpose Input & Output Number 10: Pin 4 In Intel parallel host mode, this pin serves as the active-low data-write-input strobe. In Motorola parallel host mode, this pin serves as the active-low data-strobe-input signal. In serial host mode, this pin can serve as the external-memory active-low write-enable output signal. Also in serial host mode, this pin can serve as a general purpose input or output bit. BIDIRECTIONAL - Default: INPUT CS—Host Parallel Chip Select, Host Serial SPI Chip Select: Pin 18 In parallel host mode, this pin serves as the active-low chip-select input signal. In serial host SPI mode, this pin is used as the active-low chip-select input signal. INPUT RESET—Master Reset Input: Pin 36 Asynchronous active-low master reset input. Reset should be low at power-up to initialize the CS4923/4/5/6/7/8/9 and to guarantee that the device is not active during initial power-on stabilization periods. At the rising edge of reset the host interface mode is selected contingent on the state of the RD, WR and PSEL pins. Additionally, an autoboot sequence can be initiated if a serial control mode is selected and ABOOT is held low. If reset is low all bidirectional pins are high impedance inputs. INPUT SCDIO, SCDOUT, PSEL, GPIO9—Serial Control Port Data Input and Output, Parallel Port Type Select: Pin 19 In I2C mode, this pin serves as the open-drain bidirectional data pin. In SPI mode this pin serves as the data output pin. In parallel host mode, this pin is sampled at the rising edge of RESET to configure the parallel host mode as an Intel type bus or as a Motorola type bus. In parallel host mode, after the bus mode has been selected, the pin can function as a general- purpose input or output pin. BIDIRECTIONAL - Default: INPUT In I2C mode this pin is an OPEN DRAIN I/O and requires a 4.7k Pull-Up EXTMEM, GPIO8—External Memory Chip Select or General Purpose Input & Output Number 8: Pin 21 In serial control port mode, this pin can serve as an output to provide the chip-select for an external byte-wide ROM. In parallel and serial host mode, this pin can also function as a general-purpose input or output pin. BIDIRECTIONAL - Default: INPUT INTREQ, ABOOT—Control Port Interrupt Request, Automatic Boot Enable: Pin 20 Open-drain interrupt-request output. This pin is driven low to indicate that the DSP has outgoing control data and should be serviced by the host. Also in serial host mode, this signal initiates an automatic boot cycle from external memory if it is held low through the rising edge of reset. OPEN DRAIN I/O - Requires 4.7k Ohm Pull-Up AUDATA2—Digital Audio Output 2: Pin 39 PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT DS262F2 51 CS4923/4/5/6/7/8/9 AUDATA1—Digital Audio Output 1: Pin 40 PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT AUDATA0—Digital Audio Output 0: Pin 41 PCM multi-format digital-audio data output, capable of two-, four-, or six-channel 20-bit output. This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT MCLK—Audio Master Clock: Pin 44 Bidirectional master audio clock. MCLK can be an output from the CS4923/4/5/6/7/8/9 that provides an oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs. MCLK can be an input at 128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to derive SCLK and LRCLK when SCLK and LRCLK are driven by the CS492X. BIDIRECTIONAL - Default: INPUT SCLK—Audio Output Bit Clock: Pin 43 Bidirectional digital-audio output bit clock. SCLK can be an output that is derived from MCLK to provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs, depending on the MCLK rate and the digital-output configuration. SCLK can also be an input and must be at least 48Fs or greater. As an input, SCLK is independent of MCLK. BIDIRECTIONAL - Default: INPUT LRCLK—Audio Output Sample Rate Clock: Pin 42 Bidirectional digital-audio output-sample-rate clock. LRCLK can be an output that is divided from MCLK to provide the output sample rate depending on the output configuration. LRCLK can also be an input. As an input LRCLK is independent of MCLK. BIDIRECTIONAL - Default: INPUT XMT958—SPDIF Transmitter Output: Pin 3 CMOS level output that contains a biphase-encoded clock for synchronously providing two channels of PCM digital audio or a IEC61937 compressed-data interface or both. This output typically connects to the input of an RS-422 transmitter or to the input of an optical transmitter. OUTPUT SCLKN1, STCCLK2—PCM Audio Input Bit Clock: Pin 25 Bidirectional digital-audio bit clock that is an output in master mode and an input in slave mode. In slave mode, SCLKN1 operates asynchronously from all other CS492X clocks. In master mode, SCLKN1 is derived from the CS492X internal clock generator. In either master or slave mode, the active edge of SCLKN1 can be programmed by the DSP. For applications supporting PES layer synchronization this pin can be used as STCCLK2, which provides a path to the internal STC 33 bit counter. BIDIRECTIONAL - Default: INPUT 52 DS262F2 CS4923/4/5/6/7/8/9 LRCLKN1—PCM Audio Input Sample Rate Clock: Pin 26 Bidirectional digital-audio frame clock that is an output in master mode and an input in slave mode. LRCLKN1 typically is run at the sampling frequency. In slave mode, LRCLKN1 operates asynchronously from all other CS492X clocks. In master mode, LRCLKN1 is derived from the CS492X internal clock generator. In either master or slave mode, the polarity of LRCLKN1 for a particular subframe can be programmed by the DSP. BIDIRECTIONAL - Default: INPUT SDATAN1—PCM Audio Data Input Number One: Pin 22 Digital-audio data input that can accept from one to six channels of compressed or PCM data. SDATAN1 can be sampled with either edge of SCLKN1, depending on how SCLKN1 has been configured. INPUT CMPCLK, SCLKN2—PCM Audio Input Bit Clock: Pin 28 Bidirectional digital-audio bit clock that is an output in master mode and an input in slave mode. In slave mode, SCLKN2 operates asynchronously from all other CS492X clocks. In master mode, SCLKN2 is derived from the CS492X internal clock generator. In either master or slave mode, the active edge of SCLKN2 can be programmed by the DSP. If the CDI is configured for bursty delivery, CMPCLK is an input used to sample CMPDAT. BIDIRECTIONAL - Default: INPUT CMPREQ, LRCLKN2—PCM Audio Input Sample Rate Clock: Pin 29 When the CDI is configured as a digital audio input, this pin serves as a bidirectional digital- audio frame clock that is an output in master mode and an input in slave mode. LRCLKN2 typically is run at the sampling frequency. In slave mode, LRCLKN2 operates asynchronously from all other CS492X clocks. In master mode, LRCLKN2 is derived from the CS492X internal clock generator. In either master or slave mode, the polarity of LRCLKN2 for a particular subframe can be programmed by the DSP. When the CDI is configured for bursty delivery, or parallel audio data delivery is being used, CMPREQ is an output which serves as an internal FIFO monitor. CMPREQ is an active low signal that indicates when another block of data can be accepted. BIDIRECTIONAL - Default: INPUT CMPDAT, SDATAN2—PCM Audio Data Input Number Two: Pin 27 Digital-audio data input that can accept from one to six channels of compressed or PCM data. SDATAN2 can be sampled with either edge of SCLKN2, depending on how SCLKN2 has been configured. Similarly CMPDAT is the compressed data input pin when the CDI is configured for bursty delivery. When in this mode, the CS4923/4/5/6/7/8/9 internal PLL is driven by the clock recovered from the incoming data stream. INPUT DC—Reserved: Pin 38 This pin is reserved and should be pulled up with an external 4.7k resistor. DD—Reserved: Pin 37 This pin is reserved and should be pulled up with an external 4.7k resistor. DS262F2 53 CS4923/4/5/6/7/8/9 9. PACKAGE DIMENSIONS 44L PLCC PACKAGE DRAWING e E1 E D2/E2 B D1 A1 D A INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.165 0.180 4.043 4.572 A1 0.090 0.120 2.205 3.048 B 0.013 0.021 0.319 0.533 D 0.685 0.695 16.783 17.653 D1 0.650 0.656 15.925 16.662 D2 0.590 0.630 14.455 16.002 E 0.685 0.695 16.783 17.653 E1 0.650 0.656 15.925 16.662 E2 0.590 0.630 14.455 16.002 e 0.040 0.060 0.980 1.524 54 DS262F2 • Notes •